20 MHz

AC Electrical Characteristics

(See Notes 1 and 4 and

a

Symbol and Formula

Parameter

Min

Max

Units

Notes

CKI Operating Frequency

2

20

MHz

CKI Clock Period

50

500

ns

CKI High Time

225

ns

CKI Low Time

225

ns

CPU Timing Cycle

100

ns

CPU Wait State Period

100

ns

Delay of CK2 Rising Edge 2fter CKI Falling Edge

0

55

ns

(Note 2)

Delay of CK2 Falling Edge after CKI Falling Edge

0

55

ns

(Note 2)

External UART Clock Input Frequency

25

MHz

External MICROWIREPLUS Clock Input Frequency

125

MHz

External Timer Input Frequency

091

MHz

Pulse Width for Timer Inputs

100

ns

MICROWIRE Setup Time

Master

100

ns

Slave

20

MICROWIRE Hold Time

Master

20

ns

Slave

50

MICROWIRE Output Valid Time

Master

50

ns

Slave

150

HLD Falling Edge before ALE Rising Edge

115

ns

HLD Pulse Width

110

ns

HLDA Falling Edge after HLD Falling Edge

200

ns

(Note 3)

HLDA Rising Edge after HLD Rising Edge

160

ns

Bus Float after HLDA Falling Edge

116

ns

(Note 5)

Bus Enable after HLDA Rising Edge

116

ns

(Note 5)

Address Setup Time to Falling Edge of URD

10

ns

Address Hold Time from Rising Edge of URD

10

ns

URD Pulse Width

100

ns

URD Falling Edge to Output Data Valid

0

60

ns

Rising Edge of URD to Output Data Invalid

5

35

ns

(Note 6)

RDRDY Delay from Rising Edge of URD

70

ns

UWR Pulse Width

40

ns

Input Data Valid before Rising Edge of UWR

10

ns

Input Data Hold after Rising Edge of UWR

20

ns

WRRDY Delay from Rising Edge of UWR

70

ns

This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2

clock

3