HPC16004 datasheet(10/36 Pages) NSC

10 / 36 page

Pin Descriptions

The HPC46064 is available only in 68-pin PLCC LDCC

PGA and 80-pin PQFP packages

IO PORTS

Port A is a 16-bit bidirectional IO port with a data direction

fined as an input or output When accessing external memo-

ry port A is used as the multiplexed addressdata bus

Port B is a 16-bit port with 12 bits of bidirectional IO similar

in structure to Port A Pins B10 B11 B12 and B15 are gen-

eral purpose outputs only in this mode Port B may also be

configured via a 16-bit function register BFUN to individually

allow each pin to have an alternate function

TDX

UART Data Output

CKX

UART Clock (Input or Output)

T2IO

Timer2 IO Pin

T3IO

Timer3 IO Pin

MICROWIREPLUS Output

MICROWIREPLUS Clock (Input or Output)

HLDA

Hold Acknowledge Output

TS0

Timer Synchronous Output

TS1

Timer Synchronous Output

B10

UA0

Address 0 Input for UPI Mode

B11

WRRDY Write Ready Output for UPI Mode

B12

B13

TS2

Timer Synchronous Output

B14

TS3

Timer Synchronous Output

B15

RDRDY

Read Ready Output for UPI Mode

When accessing external memory four bits of port B are

used as follows

B10

ALE

Address Latch Enable Output

B11

Write Output

B12

HBE

High Byte Enable OutputInput

(sampled at reset)

B15

Read Output

Port I is an 8-bit input port that can be read as general

purpose inputs and is also used for the following functions

NMI

Nonmaskable Interrupt Input

INT2

Maskable InterruptInput CaptureURD

INT3

Maskable InterruptInput CaptureUWR

INT4

Maskable InterruptInput Capture

MICROWIREPLUS Data Input

RDX

UART Data Input

Port D is an 8-bit input port that can be used as general

purpose digital inputs

Port P is a 4-bit output port that can be used as general

purpose data or selected to be controlled by timers 4

through 7 in order to generate frequency duty cycle and

pulse width modulated outputs

POWER SUPPLY PINS

VCC1 and

Positive Power Supply

VCC2

GND

Ground for On-Chip Logic

DGND

Ground for Output Buffers

Note

There are two electrically connected VCC pins on the chip GND and

DGND are electrically isolated Both VCC pins and both ground pins

must be used

CLOCK PINS

CKI

The Chip System Clock Input

CKO

The Chip System Clock Output (inversion of

CKI)

Pins CKI and CKO are usually connected across an external

crystal

CK2

Clock Output (CKI divided by 2)

OTHER PINS

This is an active low open drain output that

signals an illegal situation has been detected

by the WATCHDOG logic

ST1

Bus Cycle Status Output indicates first op-

code fetch

ST2

Bus Cycle Status Output indicates machine

states (skip interrupt and first instruction cy-

cle)

RESET

Active low input that forces the chip to restart

and sets the ports in a TRI-STATE mode

RDYHLD

Selected by a software bit

It’s either a

READY input to extend the bus cycle for slow-

er memories or a HOLD request input to put

the bus in a high impedance state for DMA

purposes

(No connection) do not connect anything to

this pin

EXM

External memory enable (active high) disables

internal ROM and maps it to external memory

External

interrupt

with

vector

address

FFF1FFF0 (Risingfalling edge or highlow

level sensitive) Alternately can be configured

as 4th input capture

EXUI

External active low interrupt which is internally

OR’ed with the UART interrupt with vector ad-

dress FFF3FFF2

HPC16004 Datasheet(PDF) 10 Page - National Semiconductor (TI)

HPC16004 Datasheet(HTML) 10 Page - National Semiconductor (TI)

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