AC Electrical Characteristics

(See Notes 1 and 4 and

a

Symbol and Formula

Parameter

Min

Max

Units

Notes

Delay from CKI Rising Edge to

035

ns

(Notes 1 2)

ALE Rising Edge

Delay from CKI Rising Edge to

035

ns

(Notes 1 2)

ALE Falling Edge

Delay from CK2 Rising Edge to

45

ns

(Note 2)

ALE Rising Edge

Delay from CK2 Falling Edge to

45

ns

(Note 2)

ALE Falling Edge

ALE Pulse Width

41

ns

Setup of Address Valid before

18

ns

ALE Falling Edge

Hold of Address Valid after

20

ns

ALE Falling Edge

ALE Falling Edge to RD Falling Edge

20

ns

Data Input Valid after Address Output Valid

145

ns

(Note 6)

Data Input Valid after RD Falling Edge

85

ns

RD Pulse Width

140

ns

Hold of Data Input Valid after

060

ns

RD Rising Edge

Bus Enable after RD Rising Edge

85

ns

ALE Falling Edge to WR Falling Edge

45

ns

WR Pulse Width

160

ns

Data Output Valid before WR Rising Edge

145

ns

Hold of Data Valid after WR Rising Edge

20

ns

Falling Edge of ALE to

75

ns

Falling Edge of RDY

RDY Pulse Width

100

ns

Note

40 pF

Note 1

These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall

Note 2

Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either

CKI or CKO is connected to any external logic other than the passive components of the crystal circuit

Note 3

input

Note 4

20 MHz with

one wait state programmed

Note 5

Due to emulation restrictionsactual limits will be better

Note 6

This is guaranteed by design and not tested

4