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37C672 Datasheet(PDF) 77 Page - SMSC Corporation |
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37C672 Datasheet(HTML) 77 Page - SMSC Corporation |
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77 / 173 page  Enhanced Super I/O Controller with Fast IR Datasheet SMSC FDC37C672 Page 77 Rev. 10-29-03 DATASHEET One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt. The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud). |
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