37C672 datasheet(90/173 Pages) SMSC

90 / 173 page

Enhanced Super I/O Controller with Fast IR

Datasheet

SMSC FDC37C672

Page 90

Rev. 10-29-03

DATASHEET

12.3.1 Register Definitions

The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports

are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to

avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may

be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below

lists these dependencies. Operation of the devices in modes other that those specified is undefined.

Table 12.4 - ECP Register Definitions

NAME

ADDRESS (Note 12.7)

ECP MODES

FUNCTION

data

+000h R/W

000-001

Data Register

ecpAFifo

+000h R/W

011

ECP FIFO (Address)

dsr

+001h R/W

All

Status Register

dcr

+002h R/W

All

Control Register

cFifo

+400h R/W

010

Parallel Port Data FIFO

ecpDFifo

+400h R/W

011

ECP FIFO (DATA)

tFifo

+400h R/W

110

Test FIFO

cnfgA

+400h R

111

Configuration Register A

cnfgB

+401h R/W

111

Configuration Register B

ecr

+402h R/W

All

Extended Control Register

Note 12.7 These addresses are added to the parallel port base address as selected by configuration register or

jumpers.

Note 12.8 All addresses are qualified with AEN. Refer to the AEN pin definition.

Table 12.5 - Mode Descriptions

MODE

DESCRIPTION (Note 12.9)

000

SPP mode

001

PS/2 Parallel Port mode

010

Parallel Port Data FIFO mode

011

ECP Parallel Port mode

100

EPP mode (If this option is enabled in the configuration registers)

101

(Reserved)

110

Test mode

111

Configuration mode

Note 12.9 Refer to ECR Register Description

DATA and ecpAFifo PORT

ADDRESS OFFSET = 00H

Modes 000 and 001 (Data Port)

The Data Port is located at an offset of '00H' from the base address. The data register is cleared at

initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus

on the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output

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