WM8523 datasheet(13/46 Pages) CIRRUS

13 / 46 page

Production Data

WM8523

PD, Rev 4.2, August 2013

POWER ON RESET CIRCUIT

Figure 6 Internal Power on Reset Circuit Schematic

The WM8523 includes an internal Power-On-Reset circuit, as shown in Figure 6, which is used to reset

the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD and has as

its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a minimum threshold.

Figure 7 Typical Power Timing Requirements

Figure 7 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD goes

above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee POR is asserted

low and the chip is held in reset. In this condition, all writes to the control interface are ignored. After

VMID rises to Vpord_hi and AVDD rises to Vpora_hi, POR is released high and all registers are in their default

state and writes to the control interface may take place.

On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the minimum threshold

Vpora_low.

WM8523 Datasheet(PDF) 13 Page - Cirrus Logic