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WM8741 Datasheet(PDF) 13 Page - Cirrus Logic |
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WM8741 Datasheet(HTML) 13 Page - Cirrus Logic |
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13 / 66 page  Production Data WM8741 w PD, Rev 4.3, February 2013 13 DSD AUDIO INTERFACE TIMINGS DSDCLK64 DSD[0:1] D[n] D[n-1] t DH D[n+1] t 64CY t 64L t 64H t DS t DC Figure 3 DSD Audio Timing - Normal Mode Figure 4 DSD Audio Timing - Phase Modulated Mode Test Conditions DVDD = 3.3V, GND = 0V, TA = +25 oC, fs = 44.1kHz, DSDCLK64 = 64fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information DSDCLK64 cycle time t64CY 354.3 ns DSDCLK64 pulse width high t64H 140 ns DSDCLK64 pulse width low t64L 140 ns DSD[0:1] set-up time to DSDCLK64 rising edge tDSN 20 ns DSD[0:1] hold time from DSDCLK64 rising edge tDHN 20 ns Difference in edge timing of DSD[0:1] to DSDCLK64 tDC -10 10 ns Table 3 DSD Audio Interface Timing Requirements |
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