DOC4106 datasheet(29/47 Pages) ATMEL

29 / 47 page

AT8xC51SND1C

4106F–8051–10/02

AC Characteristics

External 8-bit Bus Cycles

Definition of Symbols

Table 39. External 8-bit Bus Cycles Timing Symbol Definitions

Timings

Test conditions: capacitive load on all pins = 50 pF.

Table 40. External 8-bit Bus Cycle – Data Read AC Timings

VDD =2.7 to 3.3V, TA =-40° to +85°C

Signals

Conditions

AAddress

High

DData In

Low

ALE

Valid

Data Out

No Longer Valid

RRD

ZFloating

WWR

Symbol

Parameter

Variable Clock

Standard Mode

Variable Clock

X2 Mode

Unit

Min

Max

Min

Max

TCLCL

Clock Period

TLHLL

ALE Pulse Width

2·TCLCL-15

TCLCL-15

TAVLL

Address Valid to ALE Low

TCLCL-20

0.5·TCLCL-20

TLLAX

Address Hold after ALE Low

TCLCL-20

0.5·TCLCL-20

TLLRL

ALE Low to RD Low

3·TCLCL-30

1.5·TCLCL-30

TRLRH

RD Pulse Width

6·TCLCL-25

3·TCLCL-25

TRHLH

RD High to ALE High

TCLCL-20

TCLCL+20

0.5·TCLCL-20

0.5·TCLCL+20

TAVDV

Address Valid to Valid Data In

9·TCLCL-65

4.5·TCLCL-65

TAVRL

Address Valid to RD Low

4·TCLCL-30

2·TCLCL-30

TRLDV

RD Low to Valid Data

5·TCLCL-30

2.5·TCLCL-30

TRLAZ

RD Low to address Float

TRHDX

Data Hold After RD High

RHDZ

Instruction Float after RD

High

2·T

CLCL-25

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