DOC4106 datasheet(34/47 Pages) ATMEL

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AT8xC51SND1C

4106F–8051–10/02

Timings

Table 46. SPI Interface Master AC Timing

(2)

VDD =2.7 to 3.3V, TA =-40° to +85°C

Notes:

1. Value of this parameter depends on software.

2. Test conditions: capacitive load on all pins = 100 pF

Symbol

Parameter

Min

Max

Unit

Slave Mode

TCHCH

Clock Period

TOSC

TCHCX

Clock High Time

3.2

TOSC

TCLCX

Clock Low Time

3.2

TOSC

TSLCH,TSLCL

SS Low to Clock edge

200

TIVCL,TIVCH

Input Data Valid to Clock Edge

100

TCLIX,TCHIX

Input Data Hold after Clock Edge

100

TCLOV, TCHOV

Output Data Valid after Clock Edge

100

TCLOX,TCHOX

Output Data Hold Time after Clock Edge

TCLSH,TCHSH

SS High after Clock Edge

TIVCL,TIVCH

Input Data Valid to Clock Edge

100

TCLIX,TCHIX

Input Data Hold after Clock Edge

100

TSLOV

SS Low to Output Data Valid

130

TSHOX

Output Data Hold after SS High

130

TSHSL

SS High to SS Low

Note

(1)

TILIH

Input Rise Time

µs

TIHIL

Input Fall Time

µs

TOLOH

Output Rise Time

100

TOHOL

Output Fall Time

100

Master Mode

TCHCH

Clock Period

TOSC

TCHCX

Clock High Time

1.6

TOSC

TCLCX

Clock Low Time

1.6

TOSC

TIVCL,TIVCH

Input Data Valid to Clock Edge

TCLIX,TCHIX

Input Data Hold after Clock Edge

TCLOV, TCHOV

Output Data Valid after Clock Edge

TCLOX,TCHOX

Output Data Hold Time after Clock Edge

TILIH

Input DataRiseTime

µs

TIHIL

Input Data Fall Time

µs

TOLOH

Output Data Rise Time

TOHOL

Output Data Fall Time

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