DOC4106 datasheet(37/47 Pages) ATMEL

37 / 47 page

AT8xC51SND1C

4106F–8051–10/02

Two-wire Interface

Timings

Table 47. TWI Interface AC Timing

zVDD = 2.7 to 3.3V, TA =-40° to +85°C

Notes:

1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of

100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-up

resistor, this must be < 1

µs.

3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered

out. Maximum capacitance on bus-lines SDA and SCL = 400 pF.

4. TCLCL =TOSC = one oscillator clock period.

Waveforms

Figure 23. TWI Waveforms

Symbol

Parameter

INPUT

Min

Max

OUTPUT

Min

Max

THD; STA

Start condition hold time

14·TCLCL

(4)

4.0

µs(1)

TLOW

SCL Low Time

16·TCLCL

(4)

4.7

µs(1)

THIGH

SCLHighTime

14·TCLCL

(4)

4.0

µs(1)

TRC

SCLRiseTime

µsNote(2)

TFC

SCL Fall Time

0.3

µs0.3 µs(3)

TSU; DAT1

Data Set-up Time

250 ns

20·TCLCL(4)-TRD

TSU; DAT2

SDA Set-up Time (before repeated START condition)

250 ns

µs(1)

TSU; DAT3

SDA Set-up Time (before STOP condition)

250 ns

8·TCLCL

(4)

THD; DAT

Data Hold Time

0 ns

8·TCLCL(4) -TFC

TSU; STA

Repeated START Set-up Time

14·TCLCL(4)

4.7

µs(1)

TSU; STO

STOP condition Set-up Time

14·TCLCL(4)

4.0

µs(1)

TBUF

Bus Free Time

14·TCLCL(4)

4.7

µs(1)

TRD

SDA Rise Time

µs-(2)

TFD

SDA Fall Time

0.3

µs0.3 µs(3)

SU;DAT1

TSU;STA

Tsu;DAT2

HD;STA

THIGH

LOW

SDA

(INPUT/OUTPUT)

0.3

VDD

0.7

VDD

Tbuf

Tsu;STO

0.7

0.3

TFD

Trc

Tfc

SCL

(INPUT/OUTPUT)

THDDAT

su;DAT3

START or Repeated START Condition

START Condition

STOP Condition

Repeated START Condition

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