TMS320DM6431 datasheet(180/227 Pages) TI1

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6.13.2 McBSP Electrical Data/Timing

6.13.2.1

Multichannel Buffered Serial Port (McBSP) Timing

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 6-42. Timing Requirements for McBSP(1) (see Figure 6-27)

-3/-3Q/-3S

NO.

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

2P(2)(3)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

P - 1(4)

CLKR int

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR ext

CLKR int

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR ext

CLKR int

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR ext

CLKR int

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR ext

3.5

CLKX int

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX ext

CLKX int

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX ext

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

P = SYSCLK3 period in ns. For example, when running parts at 300 MHz, use P = 20 ns.

(3)

Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock

source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA

limitations and AC timing requirements.

(4)

This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Peripheral Information and Electrical Specifications

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