TMS320DM6431 datasheet(33/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

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SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 5, AEM[2:0] = 101)

Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., AEAW[2:0], AEM[2:0], etc.). For more details,

see Section 3.7, Multiplexed Pin Configurations

This pin is multiplexed between EMIFA (NAND) and GPIO.

EM_A[1]/(ALE)/GP[

IPD

9]/

A16

B20

I/O/Z

When used for EMIFA (NAND) , this pin is the Address Latch Enable

DVDD33

(AEAW1/PLLMS1)

output (ALE).

This pin is multiplexed between EMIFA (NAND) and GPIO.

EM_A[2]/(CLE)/GP

IPD

[8]/

B16

A20

I/O/Z

When used for EMIFA (NAND) , this pin is the Command Latch

DVDD33

(AEAW0/PLLMS0)

Enable output (CLE).

EM_WAIT/

IPU

E15

D20

I/O/Z

When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).

(RDY/BSY)

DVDD33

IPU

EM_OE

D15

D19

I/O/Z

When used for EMIFA (NAND), this pin is read enable output (RE).

DVDD33

IPU

EM_WE

E14

C19

I/O/Z

When used for EMIFA (NAND), this pin is write enable output (WE).

DVDD33

This pin is multiplexed between EMIFA (NAND) and GPIO.

For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with

NAND flash.

IPD

This is the chip select for the default boot and ROM boot modes.

EM_CS2/GP[12]

C19

C22

I/O/Z

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

This pin is multiplexed between EMIFA (NAND) and GPIO.

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with

NAND flash.

IPD

EM_CS3/GP[13]

C18

D22

I/O/Z

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

This pin is multiplexed between EMIFA (NAND) and GPIO.

For EMIFA, it is Chip Select 4 output EM_CS4 for use with NAND

flash.

IPD

EM_CS4/GP[32]

E19

H22

I/O/Z

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

This pin is multiplexed between EMIFA (NAND) and GPIO.

For EMIFA, it is Chip Select 5 output EM_CS5 for use with NAND

flash.

IPD

EM_CS5/GP[33]

F19

J22

I/O/Z

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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