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TMS320DM6431 Datasheet(PDF) 207 Page - Texas Instruments |
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TMS320DM6431 Datasheet(HTML) 207 Page - Texas Instruments |
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207 / 227 page  6.16.2 EMAC Electrical Data/Timing MRCLK 2 3 1 MTCLK 2 3 1 MRCLK (Input) 1 2 MRXD3−MRXD0, MRXDV, MRXER (Inputs) TMS320DM6431 Digital Media Processor www.ti.com SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008 Table 6-67. Timing Requirements for MRCLK (see Figure 6-37) -3/-3Q/-3S NO. 10 Mbps 100 Mbps UNIT MIN MAX MIN MAX 1 tc(MRCLK) Cycle time, MRCLK 400 40 ns 2 tw(MRCLKH) Pulse duration, MRCLK high 140 14 ns 3 tw(MRCLKL) Pulse duration, MRCLK low 140 14 ns Figure 6-37. MRCLK Timing (EMAC - Receive) Table 6-68. Timing Requirements for MTCLK (see Figure 6-37) -3/-3Q/-3S NO. 10 Mbps 100 Mbps UNIT MIN MAX MIN MAX 1 tc(MTCLK) Cycle time, MTCLK 400 40 ns 2 tw(MTCLKH) Pulse duration, MTCLK high 140 14 ns 3 tw(MTCLKL) Pulse duration, MTCLK low 140 14 ns Figure 6-38. MTCLK Timing (EMAC - Transmit) Table 6-69. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-39) -3/-3Q/-3S NO. UNIT MIN MAX 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns 2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high 8 ns (1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER. Figure 6-39. EMAC Receive Interface Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 207 |
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