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6.2 Recommended Clock and Control Signal Transition Behavior

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

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TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the

timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given

system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If

needed, external logic hardware such as buffers may be used to compensate any timing differences.

For the DDR2 memory controller interface, it is not necessary to use the IBIS models to analyze timing

characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the

DDR2 memory controller interface timings are met. See the Implementing DDR2 PCB Layout on the

TMS320DM643x DMP DMSoC Application Report (literature number SPRAAL6).

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

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Peripheral Information and Electrical Specifications

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TMS320DM6431 Datasheet(PDF) 120 Page - Texas Instruments