Preliminary Information

MT9173/74

9-147

receiving signalling information and lower speed

data between the line and the system. In DN/DUAL

mode the DNIC receives a C-channel on CDSTi

while transmitting a C-channel on CDSTo.

channel times later (halfway through the frame) a D-

channel is received on CDSTi while a D-channel is

transmitted on CDSTo. This is shown in Figure 7.

The order of the C and D bytes in DUAL port mode

can be reversed by the mode select pins. See Table

1 for a listing of the byte orientations.

The D-channel exists only in DN mode and may be

used for transferring low speed data or signalling

information over the line at 8, 16 or 64 kbit/s (by

using the DINB feature). The information passes

transparently through the DNIC and is transmitted to

or received from the line at the bit rate selected in the

Control Register.

If the bit rate is 80 kbit/s, only D0 is transmitted and

received. At 160 kbit/s, D0 and D1 are transmitted

and received. When the DINB bit is set in the Control

Register the entire D-channel is transmitted and

received in the B1-channel timeslot.

The C-channel is used for transferring control and

status information between the DNIC and the

system. The Control and Diagnostics Registers are

accessed through the C-channel. They contain

information to control the DNIC and carry out the

diagnostics as well as the HK bit to be transmitted on

the line as described in Tables 4 and 5. Bits 0 and 1

of the C-channel select between the Control and

Diagnostics Register. If these bits are 0, 0 then the

C-channel information is written to the Control

Register (Table 4).

If they are 0, 1 the C-

written to the Diagnostics Register (Table 5).

Table 4. Control Register

Notes:

Œ

Suggested use of ATTACK:

-At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms.

-At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms.



When bits 4-7 of the Control Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,

depending upon the status of bit-3.

Bit

Name

Description

0

Reg Sel-1

Register Select-1. Must be set to ’0’ to select the Control Register.

1

Reg Sel-2

Register Select-2. Must be set to ’0’ to select the Control Register.

2

DRR

Diagnostics Register Reset. Writing a "0" to this bit will cause a diagnostics register reset

to occur coincident with the next frame pulse as in the MT8972A. When this bit is a logic

"1", the Diagnostics Register will not be reset.

3

BRS

Bit Rate Select. When set to ’0’ selects 80 kbit/s. When set to ’1’, selects 160 kbit/s.

4

DINB



D-Channel in B Timeslot. When ’0’, the D-channel bits (D0 or D0 and D1) corresponding

to the selected bit rate (80 or 160 kbit/s) are transmitted during the normal D-channel bit

times. When set to ’1’, the entire D-channel (D0-D7) is transmitted during the B1-channel

timeslot on the line providing a 64 kbit/s D-channel link.

5

PSEN



Prescrambler/Deprescrambler Enable. When set to ’1’, the data prescrambler and

deprescrambler are enabled. When set to ’0’, the data prescrambler and deprescrambler

are disabled.

6

ATTACK



Convergence Speedup. When set to ’1’, the echo canceller will converge to the reflection

coefficient much faster. Used on power-up for fast convergence.

canceller will require the normal amount of time to converge to a reflection coefficient.

7

TxHK



Transmit Housekeeping. When set to ’0’, logic zero is transmitted over the line as

Housekeeping Bit. When set to ’1’, logic one is transmitted over the line as

Housekeeping Bit.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

Reg Sel-1

Reg Sel-2

DRR

BRS

DINB

PSEN

ATTACK

TxHK

Default Mode Selection (Refer to Table 4a)