PI7C7300A datasheet(46/109 Pages) PERICOM

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PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 46 OF 109

09/25/03 Revision 1.09

When a VGA-compatible device exists downstream from PI7C7300A, set the VGA

mode bit in the bridge control register in configuration space to enable VGA mode.

When PI7C7300A is operating in VGA mode, it forwards downstream those transactions

addressing the VGA frame buffer memory and VGA I/O registers, regardless of the

values of the base and limit address registers. PI7C7300A ignores transactions initiated

on the secondary interface addressing these locations.

The VGA frame buffer consists of the following memory address range:

000A 0000h–000B FFFFh

Read transactions to frame buffer memory are treated as non-prefetchable. PI7C7300A

requests only a single data transfer from the target, and read byte enable bits are

forwarded to the target bus.

The VGA I/O addresses are in the range of 3B0h–3BBh and 3C0h–3DFh I/O. These I/O

addresses are aliases every 1KB throughout the first 64KB of I/O space. This means that

address bits <15:10> are not decoded and can be any value, while address bits [31:16]

must be all 0s. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.

5.4.2

VGA SNOOP MODE

PI7C7300A provides VGA snoop mode, allowing for VGA palette write transactions to

be forwarded downstream. This mode is used when a graphics device downstream from

PI7C7300A needs to snoop or respond to VGA palette write transactions. To enable the

mode, set the VGA snoop bit in the command register in configuration space. Note that

PI7C7300A claims VGA palette write transactions by asserting DEVSEL# in VGA

snoop mode.

When VGA snoop bit is set, PI7C7300A forwards downstream transactions within the

3C6h, 3C8h and 3C9h I/O addresses space. Note that these addresses are also forwarded

as part of the VGA compatibility mode previously described. Again, address bits

<15:10> are not decoded, while address bits <31:16> must be equal to 0, which means

that these addresses are aliases every 1KB throughout the first 64KB of I/O space.

Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C7300A behaves in

the same way as if only the VGA mode bit were set.

TRANSACTION ORDERING

To maintain data coherency and consistency, PI7C7300A complies with the ordering

rules set forth in the PCI Local Bus Specification, Revision 2.2, for transactions crossing

the bridge. This chapter describes the ordering rules that control transaction forwarding

across PI7C7300A.

6.1

TRANSACTIONS GOVERNED BY ORDERING RULES

Ordering relationships are established for the following classes of transactions crossing

PI7C7300A:

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