PI7C7300A datasheet(77/109 Pages) PERICOM

77 / 109 page

PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 77 OF 109

09/25/03 Revision 1.09

14.1.14

I/O BASE REGISTER – OFFSET 1Ch

Bit

Function

Type

Description

3:0

32-bit Indicator

R/O

Read as 01h to indicate 32-bit I/O addressing

7:4

I/O Base Address

[15:12]

R/W

Defines the bottom address of the I/O address range for the bridge

to determine when to forward I/O transactions from one interface to

the other. The upper 4 bits correspond to address bits [15:12] and

are writable. The lower 12 bits corresponding to address bits [11:0]

are assumed to be 0. The upper 16 bits corresponding to address

bits [31:16] are defined in the I/O base address upper 16 bits address

Reset to 0

14.1.15

I/O LIMIT REGISTER – OFFSET 1Ch

Bit

Function

Type

Description

11:8

32-bit Indicator

R/O

Read as 01h to indicate 32-bit I/O addressing

15:12

I/O Base Address

[15:12]

R/W

Defines the top address of the I/O address range for the bridge to

determine when to forward I/O transactions from one interface to

the other. The upper 4 bits correspond to address bits [15:12] and

are writable. The lower 12 bits corresponding to address bits [11:0]

are assumed to be FFFh. The upper 16 bits corresponding to

address bits [31:16] are defined in the I/O base address upper 16 bits

address register

Reset to 0

14.1.16

SECONDARY STATUS REGISTER – OFFSET 1Ch

Bit

Function

Type

Description

20:16

Reserved

R/O

Reset to 0

66MHz Capable

R/O

Set to 1 to enable 66MHz operation on the secondary (S1 or S2)

interface

Reset to 1

Reserved

R/O

Reset to 0

Fast Back-to-

Back Capable

R/O

Set to 1 to enable decoding of fast back-to-back transactions on the

secondary (S1 or S2) interface to different targets

Reset to 0

Data Parity Error

Detected

R/WC

Set to 1 when S1_PERR# or S2_PERR# is asserted and bit 6 of

command register is set

Reset to 0

26:25

DEVSEL#

timing

R/O

DEVSEL# timing (medium decoding)

00: fast DEVSEL# decoding

01: medium DEVSEL# decoding

10: slow DEVSEL# decoding

11: reserved

Reset to 01

Signaled Target

Abort

R/WC

Set to 1 (by a target device) whenever a target abort cycle occurs on

its secondary (S1 or S2) interface

Reset to 0

PI7C7300A Datasheet(PDF) 77 Page - Pericom Semiconductor Corporation

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