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PI7C7300A Datasheet(PDF) 18 Page - Pericom Semiconductor Corporation |
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PI7C7300A Datasheet(HTML) 18 Page - Pericom Semiconductor Corporation |
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18 / 109 page  PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 18 OF 109 09/25/03 Revision 1.09 Name Pin # Type Description ENUM# R4 POD Hot Swap Status Indicator. The output of ENUM# indicates to the system that an insertion has occurred of that an extraction is about to occur. 3.7 JTAG BOUNDARY SCAN SIGNALS Name Pin # Type Description TCK V2 PIU Test Clock. Used to clock state information and data into and out of the PI7C7300A during boundary scan. TMS W1 PIU Test Mode Select. Used to control the state of the Test Access Port controller. TDO V3 PTS Test Data Output. When SCAN_EN is HIGH, it is used (in conjunction with TCK) to shift data out of the Test Access Port (TAP) in a serial bit stream. TDI W2 PIU Test Data Input. When SCAN_EN is HIGH, it is used (in conjunction with TCK) to shift data and instructions into the Test Access Port (TAP) in a serial bit stream. TRST# U3 PIU Test Reset. Active LOW signal to reset the Test Access Port (TAP) controller into an initialized state. 3.8 POWER AND GROUND Name Pin # Type Description VDD B8, C14, D5, D11, D15, E2, F18, J3, L17, N2, P19, U10, V1, V7, V15, W20 3.3V Digital Power VSS A3, A5, A8, A10, A15, A17, A20, C2, D12, D18, E3, G2, G17, H17, J2, J9, J10, J11, J12, K4, K9, K10, K11, K12, K19, L9, L10, L11, L12, M9, M10, M11, M12, M18, N1, P18, R2, T18, U2, U9, U14, U17, V17, W11, Y6, Y13 Digital Ground AVCC Y1 Analog 3.3V for PLL AGND U4 Analog Ground for PLL 3.9 PI7C7300A PBGA PIN LIST Pin # Name Type Pin # Name Type A1 S2_CBE[2] PB A2 S2_TRDY# PSTS A3 VSS - A4 S2_CBE[1] PB A5 VSS - A6 S2_AD[10] PB A7 S2_CBE[0] PB A8 VSS - A9 S2_AD[2] PB A10 VSS - A11 S1_CLKOUT[7] PTS A12 S1_REQ#[6] PIU A13 S1_CLKOUT[5] PTS A14 S1_GNT#[4] PO A15 VSS - A16 S1_REQ#[2] PIU |
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