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DAC38RF82IAAV Datasheet(PDF) 3 Page - Texas Instruments |
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DAC38RF82IAAV Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 140 page  3 DAC38RF82, DAC38RF89 www.ti.com SLASEA6B – FEBRUARY 2017 – REVISED AUGUST 2017 Product Folder Links: DAC38RF82 DAC38RF89 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Revision History (continued) • Changed input data rate From: 6666 MSPS To: 3333 MSPS for LMFSHd=41380, 2x interpolation in Table 9 ................ 31 • Changed Table 12, JESD204B frame format for LMFSHd=84111 ..................................................................................... 31 • Changed Table 14, JESD204B frame format for LMFSHd=44210 ...................................................................................... 32 • Changed Table 16, JESD204B frame format for LMFSHd = 24410 .................................................................................... 32 • Changed Table 17, JESD204B frame format for LMFSHd = 44210 .................................................................................... 32 • Changed Table 18, JESD204B frame format for LMFSHd = 88210 .................................................................................... 33 • Changed Table 19, JESD204B frame format for LMFSHd = 24410 .................................................................................... 33 • Changed Table 20, JESD204B frame format for LMFSHd=48410 ...................................................................................... 33 • Changed Table 21, JESD204B frame format for LMFSHd = 24310 .................................................................................... 33 • Changed Table 22, JESD204B frame format for LMFSHd = 48310 .................................................................................... 33 • Changed Table 23, JESD204B frame format for LMFSHd = 81180 .................................................................................... 34 • Changed Table 24, JESD204B frame format for LMFSHd = 41380 .................................................................................... 34 • Changed Table 26, JESD204B frame format for LMFSHd = 41121 .................................................................................... 35 • Added Table 27, JESD204B frame format for LMFSHd = 41121 ........................................................................................ 36 • Changed Table 38 ................................................................................................................................................................ 47 • Changed register field programming values for LMFSHd=24410, 41380, 41121 and 24310 in the Register Programming for JESD and Interpolation Mode table.......................................................................................................... 52 • Changed the bit positions of N_M1 register field From: 12-8 To: 4-0 in the Table 42 table ................................................ 53 • Changed the bit positions of N_M1’ (NPRIME_M1) register field From: 4-0 To: 12-0 in the Table 42 table ....................... 53 • Deleted ISFIRCD_ENA and ISFIRAB _ENA regsiter fields. Added ISFIR_ENA register field in Inverse Sinc Filter........... 53 • Changed the description of DAC PLL alarm in Alarm Monitoring ........................................................................................ 56 • Changed from BIST_ENA to Reserved in Table 61 ............................................................................................................ 76 • Changed from BIST_ZERO to Reserved in Table 61 ......................................................................................................... 76 • Changed the description of OUTSUM_SEL field in Table 69 ............................................................................................. 82 • Changed the junction temp and loop filter voltage range for PLL tuning in Figure 141 ..................................................... 126 Changes from Original (February 2017) to Revision A Page • Corrected the NSD values for -9dBFS in Electrical Characteristics - AC Specifications table ........................................... 15 • Added PLL/VCO characteristics table to PLL/VCO Electrical Characteristics ..................................................................... 15 • Added JESD204B clock phase register setting to Table 41 ................................................................................................ 52 • Removed descriptions for CLKJESD_DIV register from Table 41 ...................................................................................... 52 • Added JESD204B clock phase register setting to Table 42 ................................................................................................ 52 • Added information about the DAC output total current for various full scale current settings in DAC Fullscale Output Current ................................................................................................................................................................................. 58 • Changed Bit 0 of Table 128 From: Enables the GSM PLL To: Reserved.......................................................................... 119 • Changed Table 130 ........................................................................................................................................................... 121 • Changed description of SERDES_REFCLK_DIV register field in Table 131 .................................................................... 122 • Changed Bit 12:11, 6:5 and 4:2 of Table 134 ................................................................................................................... 124 |
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