SM5950AM

NIPPON PRECISION CIRCUITS INC.—16

TIMING DIAGRAMS

Input Timing (LRCI, BCKI, DI)

Figure 4. 16-bit MSB-first right-justified (IMOD0 = L, IMOD1 = L, IISI = L), BCKI = 32fsi to 64fsi

Figure 5. 20-bit MSB-first right-justified (IMOD0 = H, IMOD1 = L, IISI = L), BCKI = 40fsi to 64fsi

Figure 6. 24-bit MSB-first right-justified (IMOD0 = L, IMOD1 = H, IISI = L), BCKI = 48fsi to 64fsi

Figure 7. MSB-first left-justified, leading 16 data bits only are valid (IMOD0 = H, IMOD1 = H, IISI = L),

BCKI = 32fsi to 64fsi

Figure 8. IIS, leading 16 data bits only are valid (IMOD0 = H, IMOD1 = H, IISI = H), BCKI = 64fsi only

LRCI (fsi)

BCKI (64fsi)

DI

Lch

Rch

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LRCI (fsi)

BCKI (64fsi)

DI

20

19

18

17

Lch

Rch

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LRCI (fsi)

BCKI (64fsi)

DI

24

23

22

21

Lch

Rch

16

15

14

13

12

11

10

9

8

7

6

5

24

23

22

21

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

120

19

18

17

4

3

2

120

19

18

17

LRCI (fsi)

BCKI (64fsi)

DI

Lch

Rch

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LRCI (fsi)

BCKI (64fsi)

DI

Lch

Rch

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1