WM8734 datasheet(19/42 Pages) ETC

19 / 42 page

WM8734

Advanced Information

AI Rev 2.2 November 2001

The digital audio interface takes the data from the internal ADC digital filter and places it on the

ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital

filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls

whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are

synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low

transition. BCLK maybe an input or an output dependent on whether the device is in master or slave

mode. Refer to the MASTER/SLAVE OPERATION section.

The digital audio interface also receives the digital audio data for the internal DAC digital filters on the

DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters

with left and right channels multiplexed together. DACLRC is an alignment clock that controls

whether Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous

with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always

an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master

or slave mode. Refer to the MASTER/SLAVE OPERATION section

There are four digital audio interface formats accommodated by the WM8734. These are shown in

the figures below. Refer to the Electrical Characteristic section for timing information.

Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR

or DACLRC transition.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2

n-1

LSB

MSB

n-2

n-1

LSB

MSB

Figure 16 Left Justified Mode

2S mode is where the MSB is available on the 2nd rising edge of BCLK following a LRCLK transition.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2

n-1

LSB

MSB

n-2

n-1

LSB

MSB

1 BCLK

Figure 17 I

2S Mode

Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a LRCLK

transition, yet MSB is still transmitted first.

WM8734 Datasheet(PDF) 19 Page - List of Unclassifed Manufacturers

WM8734 Datasheet(HTML) 19 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL