WM8734 datasheet(20/42 Pages) ETC

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WM8734

Advanced Information

AI Rev 2.2 November 2001

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 18 Right Justified Mode

DSP mode is where the left channel MSB is available on either the 1

st or 2nd rising edge of BCLK

(selectable by LRP) following a LRC transition high.

Right channel data immediately follows left

channel data.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

n-2 n-1

LSB

MSB

n-2 n-1

1 BCLK

Input Word Length (IWL)

Note: Input word length is defined by the IWL register, LRP = 1

1/fs

Figure 19 DSP Mode

In all modes DACLRC and ADCLRC must always change on the falling edge of BCLK, refer to Figure

16, Figure 17, Figure 18 and Figure 19. Operating the digital audio interface in DSP mode allows

ease of use for supporting the various sample rates and word lengths. The only requirement is that

all data is transferred within the correct number of BCLK cycles to suit the chosen word length.

In order for the digital audio interface to offer similar support in the three other modes (Left Justified,

2S and Right Justified), the DACLRC, ADCLRC and BCLK frequencies, continuity and mark-space

ratios need more careful consideration.

In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio.

BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for

each DACLRC/ADCLRC transition to clock the chosen data word length.

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