X5643P datasheet(8/19 Pages) XICOR

8 / 19 page

X5643/X5645

Characteristics subject to change without notice.

8 of 19

REV 1.1.1 3/5/01

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For the page write operation (byte or page write) to be

completed, CS can only be brought HIGH after bit 0 of

the last data byte to be written is clocked in. If it is

brought HIGH at any other time, the write operation will

not be completed (Figure 4).

To write to the status register, the WRSR instruction is

followed by the data to be written (Figure 5). Data bits

0 and 1 must be “0”.

While the write is in progress following a status register or

EEPROM sequence, the status register may be read to

check the WIP bit. During this time the WIP bit will be high.

OPERATIONAL NOTES

The device powers-up in the following state:

– The device is in the low power standby state.

– A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

– SO pin is high impedance.

– The write enable latch is reset.

– The ﬂag bit is reset.

– Reset signal is active for tPURST.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– A WREN instruction must be issued to set the write

enable latch.

–CS must come HIGH at the proper clock count in

order to start a nonvolatile write cycle.

Figure 6. Read Status Register Sequence

Figure 7. Write Enable Latch Sequence

0123456789

11 12 13 14

76543210

Data Out

SCK

MSB

High Impedance

Instruction

01234567

SCK

High Impedance

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