IC-PVL datasheet(21/33 Pages) ICHAUS

21 / 33 page

preliminary

iC-PVL LINEAR/OFF-AXIS

BATTERY-BUFFERED HALL MULTITURN ENCODER

Rev B3, Page 21/33

MULTITURN COUNTER

In battery buffered serial interface mode (SEL = low) or

I2C slave mode, and as long as the system is powered

up correctly (i.e. via battery or main supply), iC-PVL

will count the multiturn position. Note that there is no

counter overflow handling (positive or negative direc-

tion).

The internal counter (MT_COUNT) is 40 bits wide and

thus can count up to 240 − 1 revolutions. In SSI mode,

the output bit width is defined by MT_BW, so that

2MT_BW − 1 revolutions can be counted. Position read-

-out via SSI or I2C is exclusive, please refer to I2C

SLAVE MODE on Page 23.

The counter can be preloaded to a position defined by

configuration parameter MT_PREL (Table 26).Refer to

Table 19 for the configuration of the counter bit width.

The multiturn counter value as well as the configura-

tion RAM are secured by an eight bit CRC. Refer to

chapter I2C MULTIMASTER INTERFACE AND CRC

PROTECTION for details.

MT_PREL

Addr. 0x06 - 0x0A;

Code

Value

0x0000000000

0x0000000001

...

0x00000000FF

255

...

0xFFFFFFFFFF

240 − 1

Table 26: Multiturn preload value

PARALLEL ENCODER MODE (SEL = HIGH)

The input/output signals in parallel encoder mode are

described in Figure 11. A start pulse on the PRE line

triggers the Hall sensor signal acquisition. The current

position is sent as a three bit complementary word via

pins P0, N0 to P2, N2. In this mode, the iC-PVL oper-

ates with a single power supply on pin VBAT. Pin VDD

must be tied to GND, and the select input SEL must be

connected to a logic high level, e.g. VBAT (see circuit

in Figure 5).

start

cycle

VBAT

PRE

SEL

process

Sector 101

Sector 011

VDD

Figure 11: Line signals for parallel encoder mode (3 bit complementary P0-P2 and N0-N2)

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