AD7734 datasheet(23/32 Pages) AD

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AD7734

Rev. 0 | Page 23 of 32

Reset

The AD7734 can be reset by the RESET pin or by writing a reset

sequence to the AD7734 serial interface.

The reset sequence is N × 0 + 32 × 1, which could be the data

sequence 00h + FFh + FFh + FFh + FFh in a byte-oriented

interface. The AD7734 also features a power-on reset with a

trip point of 2 V and goes to the defined default state after

power-on.

It is the system designer’s responsibility to prevent an unwanted

write operation to the AD7734. The unwanted write operation

could happen when a spurious clock appears on the SCLK while

the CS pin is low. It should be noted that on system power-on, if

the AD7734 interface signals are floating or undefined, the part

can be inadvertently configured into an unknown state. This

could be easily overcome by initiating either a hardware reset

event or a 32 ones reset sequence as the first step in the system

configuration.

Access the AD7734 Registers

All communications to the part start with a write operation to

the communications register followed by either reading or

writing the addressed register.

In a simultaneous read-write interface (such as SPI), write 0 to

the AD7734 while reading data.

Figure 16 shows the AD7734 interface read sequence for the

ADC status register.

DIN

SCLK

DOUT

WRITE

COMMUNICATIONS

READ

ADC STATUS

Figure 16. Serial Interface Signals—Registers Access

Single Conversion and Reading Data

When the mode register is being written, the ADC status byte is

cleared and the RDY pin goes high, regardless of its previous

state. When the single conversion command is written to the

mode register, the ADC starts the conversion on the channel

selected by the address of the mode register. After the

conversion is completed, the data register is updated, the mode

the RDY pin goes low. The RDY bit is reset and the RDY pin

returns high when the relevant channel data register is

being read.

Figure 17 shows the digital interface signals executing a single

conversion on Channel 0, waiting for the RDY pin to go low,

and reading the Channel 0 data register.

DIN

SCLK

DOUT

WRITE

COMMUNICATIONS

WRITE

MODE

RDY

CONVERSION TIME

READ DATA REGISTER

38h

40h

48h

(00h)

DATA

WRITE

COMMUNICATIONS

Figure 17. Serial Interface Signals—Single Conversion Command and 16-Bits Data Reading

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