AD7734

Rev. 0 | Page 28 of 32

Multiplexer, Conversion, and Data Output Timing

The specified conversion time includes one or two settling and

sampling periods and a scaling time.

With chopping enabled (Figure 25), a conversion cycle starts

with a settling time of 43 MCLK cycles or 44 MCLK cycles

(~7 µs with a 6.144 MHz MCLK) to allow the circuits following

the multiplexer to settle. The sigma-delta modulator then

samples the analog signals and the digital filter processes the

digital data stream. The sampling time depends on FW, i.e., on

the channel conversion time register contents. After another

settling of 42 MCLK cycles (~6.8 µs), the sampling time is

repeated with a reversed (chopped) analog input signal. Then,

during the scaling time of 163 MCLK cycles (~26.5 µs), the two

results from the digital filter are averaged, scaled using the

calibration registers, and written into the channel data register.

With chopping disabled (Figure 26), there is only one sampling

time preceded by a settling time of 43 MCLK cycles or

44 MCLK cycles and followed by a scaling time of

163 MCLK cycles.

The RDY pin goes high during the scaling time, regardless of its

previous state. The relevant RDY bit is set in the ADC status

register and in the channel status register, and the RDY pin goes

low when the channel data register is updated and the channel

conversion cycle is finished. If in continuous conversion mode,

the part will automatically continue with a conversion cycle on

the next enabled channel.

Note that every channel can be configured independently for

conversion time and chopping mode. The overall cycle and

effective per channel data rates depend on all enabled

channel settings.

Sigma-Delta ADC

The AD7734 core consists of a charge balancing sigma-delta

modulator and a digital filter. The architecture is optimized for

fast, fully settled conversion. This allows for fast channel-to-

channel switching while maintaining inherently excellent

linearity, high resolution, and low noise.

– CHANNEL 1

SCALING

TIME

SAMPLING

TIME

+ CHANNEL 1

SAMPLING

TIME

SETTLING

TIME

MULTIPLEXER

– CHANNEL 0

RDY

SETTLING

TIME

CONVERSION TIME

Figure 25. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled

SCALING

TIME

CHANNEL 1

SAMPLING

TIME

MULTIPLEXER

CHANNEL 0

RDY

SETTLING

TIME

CONVERSION TIME

Figure 26. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled