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AD7734

Analog Input’s Extended Voltage Range

The AD7734 output data code span corresponds to the nominal

input voltage range. The ADC is functional outside the nominal

input voltage range, but the performance might degrade. The

sigma-delta modulator was designed to fully cover a ±11.6 V

analog input voltage; outside this range, the performance might

degrade more rapidly. The adjacent channels are not affected by

up to ±16.5 V analog input voltage (Figure 8).

When the CLAMP bit in the mode register is set to 1, the

channel data register will be digitally clamped to either all 0s or

all 1s when the analog input voltage goes outside the nominal

input voltage range.

As shown in Table 16 and Table 17, when CLAMP = 0, the data

reflects the analog input voltage outside the nominal voltage

range. In this case, the SIGN and OVR bits in the channel status

to decode the actual conversion result.

Note that the OVR bit in the channel status register is generated

digitally from the conversion result and indicates the sigma-

delta modulator (nominal) overrange. The OVR bit DOES NOT

indicate exceeding the AIN pin’s absolute voltage limits

Table 16. Extended Input Voltage Range, Nominal

Voltage Range ±10 V, 16 Bits, CLAMP = 0

Input (V)

Data (hex)

SIGN

OVR

11.60039

147B

10.00061

0001

10.00031

0000

10.00000

FFFF

0.00031

8001

0.00000

8000

–0.00031

7FFF

–10.00000

0000

–10.00031

FFFF

–10.00061

FFFE

–11.60040

EB85

Table 17. Extended Input Voltage Range, Nominal

Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0

Input (V)

Data (hex)

SIGN

OVR

11.60006

28F5

10.00031

0001

10.00015

0000

10.00000

FFFF

0.00015

0001

0.00000

0000

–0.00015

0000

Chopping

With chopping enabled, the multiplexer repeatedly reverses the

ADC inputs. Every output data result is then calculated as an

average of two conversions, the first with the positive and the

second with the negative offset term included. This effectively

removes any offset error of the input buffer and sigma-delta

modulator.

However, chopping is applied only behind the input resistor

divider stage; therefore, chopping does not eliminate the offset

error and drifts caused by the resistors. Figure 24 shows the

channel signal chain with chopping enabled.

DIGITAL

INTERFACE

CHOP

fMCLK/2

BUFFER

MULTIPLEXER

DIGITAL

FILTER

SCALING

ARITHMETIC

(CALIBRATIONS)

OUTPUT DATA

AT THE SELECTED

DATA RATE

AIN

BIASHI

BIAS

BIASLO

Σ−∆

MODULATOR

Figure 24. Channel Signal Chain Diagram with Chopping Enabled

Rev. 0 | Page 27 of 32

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