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LTC1966

sn1966 1966fas

Obviously, the effect of crest factor is somewhat simplified

above given the factor of two difference based on a

subjective description of the waveform type. The results

will vary somewhat based on actual crest factor and

waveform dynamics and the type of filtering used. The

above method is conservative for some cases and about

right for others.

The LTC1966 works well with signals whose crest factor

is 4 or less. At higher crest factors, the internal

∆Σ

modulator will saturate, and results will vary depending on

the exact frequency, shape and (to a lesser extent) ampli-

tude of the input waveform. The output voltage could be

higher or lower than the actual RMS of the input signal.

The

∆Σ modulator may also saturate when signals with

crest factors less than 4 are used with insufficient averag-

ing. This will only occur when the output droops to less

than 1/4 of the input voltage peak. For instance, a DC-

coupled pulse train with a crest factor of 4 has a duty cycle

of 6.25% and a 1VPEAK input is 250mVRMS. If this input is

50Hz, repeating every 20ms, and CAVE = 1µF, the output

will droop during the inactive 93.75% of the waveform.

This droop is calculated as:

MIN

RMS

INACTIVE TIME













−







1–

2 • Z

• C

OUT

AVE

For the LTC1966, whose output impedance (ZOUT) is

85k

Ω, this droop works out to –5.22%, so the output

would be reduced to 237mV at the end of the inactive

portion of the input. When the input signal again climbs to

1VPEAK, the peak/output ratio is 4.22.

With CAVE = 10µF, the droop is only – 0.548% to 248.6mV

and the peak/output ratio is just 4.022, which the LTC1966

has enough margin to handle without error.

For crest factors less than 3.5, the selection of CAVE as

previously described should be sufficient to avoid this

droop and modulator saturation effect. But with crest

factors above 3.5, the droop should also be checked for

each design.

Error Analyses

Once the RMS-to-DC conversion circuit is working, it is

time to take a step back and do an analysis of the accuracy

APPLICATIO S I FOR ATIO

of that conversion. The LTC1966 specifications include

three basic static error terms, VOOS, VIOS and GAIN. The

output offset is an error that simply adds to (or subtracts

from) the voltage at the output. The conversion gain of the

LTC1966 is nominally 1.000 VDCOUT/VRMSIN and the gain

error reflects the extent to which this conversion gain is

not perfectly unity. Both of these affect the results in a

fairly obvious way.

Input offset on the other hand, despite its conceptual

simplicity, effects the output in a nonobvious way. As its

name implies, it is a constant error voltage that adds

directly with the input. And it is the sum of the input and

VIOS that is RMS converted.

This means that the effect of VIOS is warped by the

nonlinear RMS conversion. With 0.2mV (typ) VIOS, and a

200mVRMS AC input, the RMS calculation will add the DC

and AC terms in an RMS fashion and the effect is

negligible:

VOUT = √(200mV AC)2 + (0.2mV DC)2

= 200.0001mV

= 200mV + 1/2ppm

But with 10

× less AC input, the error caused by VIOS is

100

× larger:

VOUT = √(20mV AC)2 + (0.2mV DC)2

= 20.001mV

= 20mV + 50ppm

This phenomena, although small, is one source of the

LTC1966’s residual nonlinearity.

On the other hand, if the input is DC coupled, the input

offset voltage adds directly. With +200mV and a +0.2mV

VIOS, a 200.2mV output will result, an error of 0.1% or

1000ppm. With DC inputs, the error caused by VIOS can be

positive or negative depending if the two have the same or

opposing polarity.

The total conversion error with a sine wave input using the

typical values of the LTC1966 static errors is computed as

follows:

VOUT = (√(500mV AC)2 + (0.2mV DC)2) • 1.001 + 0.1mV

= 500.600mV

= 500mV + 0.120%

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