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LTC3830 Datasheet(PDF) 13 Page - Linear Technology |
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LTC3830 Datasheet(HTML) 13 Page - Linear Technology |
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13 / 24 page  13 LTC3830/LTC3830-1 sn3830 3830fs Figure 12 shows a typical 5V to 3.3V application using a doubling charge pump to generate PVCC1. Power MOSFETs Two N-channel power MOSFETs are required for most LTC3830 circuits. These should be selected based primarily on threshold voltage and on-resistance consid- erations. Thermal dissipation is often a secondary con- cern in high efficiency designs. The required MOSFET threshold should be determined based on the available power supply voltages and/or the complexity of the gate drive charge pump scheme. In 3.3V input designs where an auxiliary 12V supply is available to power PVCC1 and PVCC2, standard MOSFETs with RDS(ON) specified at VGS = 5V or 6V can be used with good results. The current drawn from this supply varies with the MOSFETs used and the LTC3830’s operating frequency, but is generally less than 50mA. LTC3830 applications that use 5V or lower VIN voltage and a doubling/tripling charge pump to generate PVCC1 and PVCC2, do not provide enough gate drive voltage to fully enhance standard power MOSFETs. Under this condition, the effective MOSFET RDS(ON) may be quite high, raising the dissipation in the FETs and reducing efficiency. Logic level FETs are the recommended choice for 5V or lower voltage systems. Logic level FETs can be fully enhanced with a doubler/tripling charge pump and will operate at maximum efficiency. After the MOSFET threshold voltage is selected, choose the RDS(ON) based on the input voltage, the output voltage, allowable power dissipation and maximum output current. In a typical LTC3830 circuit, operating in continuous mode, the average inductor current is equal to the output load current. This current flows through either Q1 or Q2 with the power dissipation split up according to the duty cycle: DC Q V V DC Q V V VV V OUT IN OUT IN IN OUT IN () () – – 1 21 = == The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R. R P DC Q I VP VI R P DC Q I VP VV I DS ON Q MAX Q LOAD IN MAX Q OUT LOAD DS ON Q MAX Q LOAD IN MAX Q IN OUT LOAD () () () () () () () • ( ) • •( ) () • ( ) • (– ) • ( ) 1 1 2 1 2 2 2 2 2 2 1 2 == == APPLICATIO S I FOR ATIO LTC3830 3830 F09a + DZ 12V 1N5242 Q1 LO Q2 COUT VOUT 0.1 µF PVCC2 OPTIONAL USE FOR VIN ≥ 7V MBR0530T1 PVCC1 G1 G2 VIN Figure 9a. Doubling Charge Pump LTC3830 SS 3830 F09b + Q1 Q3 BSS284 R1 1M LO Q2 COUT VOUT 0.1 µF PVCC2 10 µF D1 D2 PVCC1 G1 G2 VIN R2 200k Q4 3906 Figure 9b. Duty Cycle Clamp Circuit |
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