AD7770ACPZ datasheet(39/98 Pages) AD

39 / 98 page

AD7770

Data Sheet

Rev. C | Page 38 of 97

CONTROLLING THE AD7770

The AD7770 can be controlled using either pin control mode or

SPI control mode.

Pin control mode allows the AD7770 to be hardwired to predefined

settings that offer a subset of the overall functionality of the

AD7770. In this mode, the SRC and diagnostic features or

extended errors source are not available.

Controlling the AD7770 over the SPI allows the user access to

the full monitoring, diagnostic, and Σ-Δ control functionality.

SPI control offers additional functionality such

as offset, gain, and phase correction per channel, in addition to

access to the flexible SRC to achieve a coherent sampling.

See Table 13 for more details about these different configurations.

PIN CONTROL MODE

In pin control mode, the AD7770 is configured at power-up

based on the level of the mode pins, MODE0, MODE1, MODE2,

and MODE3. These four pins set the following functions on the

AD7770: the mode of operation, the decimation rate/ODR, the

PGA gain, and the reference source, as shown in Table 14.

Due to the limited number of mode pins and the number of

options available, the PGA gain control is grouped into blocks

of 4, and the ODR is selected for the maximum value defined by

the decimation rate; ODR (kHz) = 2048/decimation for high

resolution mode, and ODR (kHz) = 512/decimation for low

power mode.

Depending on the mode selected, the device is configured to

use an external or an internal reference.

The conversion data can be read back using the SPI or the data

output interface, as shown in Table 13. If the data output interface

is used to read back the data from the conversions, the number of

DOUTx lines enabled and the number of clocks required for

the Σ-Δ data transfer are determined by the logic level of the

CONVST_SAR, FORMAT0, and FORMAT1 pins. In this case,

the DCLK2, DCLK1, and DCLK0 pins select the Σ-Δ output

interface and control the DCLKx divide function, which is a

submultiple of MCLK, as shown in Table 15. The DCLKx divide

function sets the frequency of the data output interface DCLKx

signal. The DCLK minimum frequency depends on the decima-

tion rate and operation mode. See the Data Output Interface

section for more details about the minimum DCLKx frequency.

All the pins that define the AD7770 configuration mode are

reevaluated each time the SYNC_IN pin is pulsed. The typical

connection diagram for pin control mode is shown in Figure 98.

Table 13. Format of the Data Interface

CONVST_SAR State

FORMAT1

FORMAT0

Control Mode

Data Output Mode

SPI output

SPI

Defined in Register 0x014

DOUT0, Channel 0 and Channel 1

DOUT1, Channel 2 and Channel 3

DOUT2, Channel 4 and Channel 5

DOUT3, Channel 6 to Channel 7

DOUT0, Channel 0 to Channel 3

DOUT1, Channel 4 to Channel 7

DOUT0, Channel 0 to Channel 7

SPI

Defined in Register 0x014

Table 14. Pin Mode Options

Pin State

Decimation

Rate

Power Mode

PGA Gain Channel

Reference

Source

MODE3

MODE2

MODE1

MODE0

Channel 0 to

Channel 3

Channel 4 to

Channel 7

1024

High resolution

External

512

High resolution

External

256

High resolution

External

128

High resolution

External

High resolution

External

512

High resolution

External

256

High resolution

External

128

High resolution

External

High resolution

External

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