AD7770ACPZ datasheet(58/98 Pages) AD

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Data Sheet

AD7770

Rev. C | Page 57 of 97

Minimum DCLKx Frequency

Select the DCLKx frequency ratio in such a way that the data is

completely shifted out before a new conversion is completed;

otherwise the previous conversion is overwritten and the transmis-

sion becomes corrupt. The minimum DCLKx frequency ratio is

defined by the decimation rate, the operation mode, and the

lines enabled on the DOUT3 to DOUT0 data interfaces as

described in the following equations.

In standalone mode and high resolution mode,

DCLKMIN_RATIO < Decimation/(8 × CHANNELS_PER_DOUT)

In standalone mode and low power mode,

DCLKMIN_RATIO < Decimation/(4 × CHANNELS_PER_DOUT)

In daisy-chain mode and high resolution mode,

DCLKMIN_RATIO < Decimation/(8 × Devices × DOUTx Channels)

In daisy-chain mode and low power mode,

DCLKMIN_RATIO < Decimation/(4 × Devices × DOUTx Channels)

As an example, when operating in master interface mode,

FORMATx = 01, the DOUT0 and DOUT1 pins shift out four

Σ-Δ channels each and, assuming a maximum output rate in

high resolution mode, the decimation = 128.

DCLKMIN < 128/(8 × 4) = 4

If the DCLKMIN_RATIOis selected above the necessary minimum, a

Logic 0 is continuously transmitted until a new sample is available.

An example in daisy-chain mode, assuming FORMATx = 01,

and with three devices connected and a decimation rate of 256

in high resolution mode, is as follows:

DCLKMIN_RATIO < 256/(8 × 3 × 4) = 2.66 = 2

The different ratios are summarized in Table 39.

Table 39. Available DCLK Ratios

DCLK_CLK_DIV (SPI Control Mode),

DCLKx (Pin Control Mode)

DCLKx Ratio

000

001

010

011

100

101

110

111

128

There are maximum achievable ODRs and minimum DCLKx

frequencies required for a given DOUTx pin configuration, as

shown in Table 40 and Table 41.

Table 40. Maximum ODRs and Minimum DCLKx Frequencies

in High Resolution Mode

Decimation

Rate

ODR

(kSPS)

Minimum DCLKx (kHz)

1 × DOUTx

2 × DOUTx

4 × DOUTx

4095

0.500122

128

2048

256

128

1024

512

256

128

512

1024

512

256

2048

1024

512

128

4096

2048

1024

8192

4096

2048

Table 41. Maximum ODRs and Minimum DCLKx Frequencies

in Low Power Mode

Decimation

Rate

ODR

(kSPS)

Minimum DCLKx (kHz)

1 × DOUTx

2 × DOUTx

4 × DOUTx

2048

0.25

1024

0.5

128

512

256

128

256

512

256

128

1024

512

256

2048

1024

512

If the AD7770 operates in SPI control mode, it is possible to

adjust the DOUTx strength, which can be selected in the

DOUT_DRIVE_STR bits, as described in Table 42.

Table 42. DOUTx Strength

DOUT_DRIVE_STR

Mode

Nominal

Strong

Weak

Extra strong

SPI

The SPI gives the user flexibility to read the conversion from the Σ-

Δ ADC where the processor or microcontroller is the master.

When a new conversion is completed, the DRDY signal is

toggled to indicate that data can be accessed. When DRDY

toggles, the internal channel counter is reset and the next SPI

read originates from Channel 0 again. Conversely, after the last

channel data is read, all successive reads before the next DRDY

signal originate from Channel 7 (LSB).

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