AD7770ACPZ datasheet(43/98 Pages) AD

43 / 98 page

AD7770

Data Sheet

Rev. C | Page 42 of 97

If the Σ-Δ reference is updated, it is recommended to apply a

pulse on the SYNC_IN pin to remove invalid samples during

the transition of the reference

Decimation

The decimation defines the sampling frequency as follows:

•

In high resolution mode, the sampling frequency = MCLK/

(4 × decimation)

•

In low power mode, the sampling frequency = MCLK/

(8 × decimation)

Refer to the SRC section for more information.

GPIOx Pins

If the AD7770 operates in SPI control mode, the mode pins

operate as GPIOx pins, as shown in Figure 100. The GPIOx pins

can be configured as inputs or outputs in any order.

MAP

GPIO0

GPIO1

GPIO2

Figure 100. GPIOx Pin Functionality

Configuration control and readback of the GPIOx pins are set

via Bits[2:0] in the GPIO_CONFIG register (0 = input, 1 = output)

and the GPIO_DATA register. Among other uses, the GPIOs

can control an external mux connected to the auxiliary inputs of

the SAR ADC. Use this mux to verify the results on the Σ-Δ ADCs.

In addition, the GPIOx pins can be used to externally trigger a

new decimation rate. Refer to the SRC section for more

information about this functionality.

Σ-Δ Reference Configuration

The AD7770 can operate with internal or external references. In

addition, for diagnostic purposes, the analog supply can be used

as a reference, as shown in Table 19. REFx−/REFx+ allows the

selection of a voltage reference where the REFx+ is lower

voltage than REFx− pin.

Table 19. Σ-Δ References

Setting for

ADC_MUX_CONFIG,

Bits[7:6]

Channel 0 to

Channel 3

Channel 4 to

Channel 7

REF1+/REF1−

REF2+/REF2−

Internal reference

AVDD1A/AVSS1A

AVDD1B/AVSS1B

REF1−/REF1+

REF2−/REF2+

Reference buffer operation is described in Table 20. The

selected reference and buffer operation mode affect all

channels.

If the Σ-Δ reference is updated, it is recommended to apply a

pulse on the SYNC_IN pin to remove invalid samples during

the transition of the reference.

Table 20. Reference Buffer Operation Modes

Reference Buffer

Operation Mode

REFx+

REFx−

Enabled

BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 0

BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 0

Precharged

BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 1

BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 1

Disabled

BUFFER_CONFIG_1, Bit 4 = 0

BUFFER_CONFIG_1, Bit 3 = 0

Table 21. Additional Disable Power-Down Blocks

Block

Notes

VCM

GENERAL_USER_CONFIG_1, Bit 5

Enable by default

Reference Buffer

BUFFER_CONFIG_1, Bits[4:3]

Precharged mode by default

Internal Reference Buffer

GENERAL_USER_CONFIG_1, Bit 4

Disable by default

Σ-Δ Channel

CH_DISABLE, Bits[7:0]

All channels enable

SAR

GENERAL_USER_CONFIG_1, Bit 3

Disable by default

Internal Oscillator

GENERAL_USER_CONFIG_1, Bit 2

Enable by default

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