MT9D011 datasheet(6/61 Pages) MICRON

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MT9D011

2-MEGAPIXEL DIGITAL IMAGE SENSOR

PRELIMINARY

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN

General Description

The Micron® Imaging MT9D011 is an oversize

UXGA-format CMOS active-pixel digital image sensor

with a pixel array of 1632H x 1216V. It incorporates

sophisticated on-chip camera functions such as win-

dowing, mirroring, row skip modes, and snapshot

mode. It is programmable through a simple two-wire

serial interface and achieves very low power consump-

tion.

The 2-megapixel CMOS image sensor features Digi-

talClarity—Micron’s breakthrough low-noise CMOS

imaging technology that achieves CCD image quality

(based on signal-to-noise ratio and low-light sensitiv-

ity) while maintaining the inherent size, cost, and inte-

gration advantages of CMOS.

When operated in default mode, the sensor gener-

ates a UXGA image at 15 frames per second (fps). An

on-chip ADC generates a 10-bit value for each pixel.

The pixel data is output on a 10-bit output bus and

qualified by an output data clock (PIXCLK), together

with LINE_VALID and FRAME_VALID signals. A FLASH

output strobe is provided to allow an external Xenon or

LED light source to synchronize with the sensor expo-

sure time. The sensor can be programmed by the user

to control the frame size, exposure, gain setting, and

other parameters.

Figure 1: Block Diagram

Introduction

The MT9D011 is a progressive-scan sensor that gen-

erates a stream of pixel data qualified by LINE_VALID

and FRAME_VALID signals. An on-chip PLL generates

the master clock from an input clock of 4 MHz to 40

MHz. In default mode, the data rate (pixel clock) is the

same as the master clock frequency, which means that

one pixel is generated every master clock cycle. The

sensor block diagram is shown in Figure 1.

The core of the sensor is an active-pixel array. The

timing and control circuitry sequences through the

rows of the array, resetting and then reading each row.

In the time interval between resetting a row and read-

ing that row, the pixels in that row integrate incident

light. The exposure is controlled by varying the time

interval between reset and readout. After a row is read,

the data from the columns is sequenced through an

analog signal chain (providing offset correction and

gain), and then through an ADC. The output from the

ADC is a 10-bit value for each pixel in the array. The

pixel array contains optically active and light-shielded

“black” pixels. The black pixels are used to provide

data for on-chip offset correction algorithms (“black

level” control).

The sensor contains a set of 16-bit control and sta-

tus registers that can be used to control many aspects

of the sensor operations. These registers can be

accessed through a two-wire serial interface. In this

document, registers are specified either by name (e.g.,

column start) or by register address (e.g., Reg0x04).

Fields within a register are specified by bit or by bit

range (e.g., Reg0x20[0] or Reg0x0B[13:0]). The control

and status registers are described in “Registers” on

page 17.

The output from the sensor is a Bayer pattern: alter-

nate rows are a sequence of either green/red pixels or

blue/green pixels. The offset and gain stages of the

analog signal chain provide per-color control of the

pixel data.

Active-Pixel Sensor

(APS) Array

UXGA

1600H x 1200V

Serial

I/O

Data

Out

Sync

Signals

Control Register

Analog Processing

ADC

Timing and Control

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