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MT9D011 Datasheet(PDF) 21 Page - Micron Technology

Part # MT9D011
Description  1/3-INCH 2-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
PDF  61 Pages
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT9D011 Datasheet(HTML) 21 Page - Micron Technology

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MT9D011
2-MEGAPIXEL DIGITAL IMAGE SENSOR
PRELIMINARY
09005aef81516da4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN
21
©2004 Micron Technology, Inc. All rights reserved.
Register Description
Table 7 provides a detailed description of the regis-
ters. Bit fields that are not identified in the table are
read only.
Double-Buffered Registers
Some sensor settings cannot be changed during
frame readout. For example, changing row width
Reg0x03 part way through frame readout results in
inconsistent LINE_VALID behavior. To avoid this, the
MT9D011 double buffers many registers by imple-
menting a “pending” and a “live” version. Reads and
writes access the pending register. The live register
controls the sensor operation.
The value in the pending register is transferred to a
live register at a fixed point in the frame timing, called
“frame start.” Frame start is defined as the point at
which the first dark row is read out. By default, this
occurs ten row times before FRAME_VALID goes high.
Reg0x22 enables the dark rows to be shown in the
image, but this has no effect on the position of frame
start.
To determine which registers or register fields are
double-buffered in this way, see Table 7, the “sync’d-
to-frame-start” column.
Reg0x0D[15] can be used to inhibit transfers from
the pending to the live registers. This control bit
should be used when making many register changes
that must take effect simultaneously.
Bad Frames
A bad frame is a frame where all rows do not have
the same integration time, or where offsets to the pixel
values changed during the frame.
Many changes to the sensor register settings can
cause a bad frame. For example, when row width
Reg0x03 is changed, the new register value does not
affect sensor behavior until the next frame start. How-
ever, the frame that would be read out at that frame-
start has been integrated using the old row width. Con-
sequently, reading it out using the new row width
results in a frame with an incorrect integration time.
By
default,
most
bad
frames
are
masked:
LINE_VALID and FRAME_VALID are inhibited for
these frames so that the vertical blanking time
between frames is extended by the frame time.
To determine which register or register field
changes can produce a bad frame, see Table 7, the
“bad frame” column, and these notations:
• N—No. Changing the register value does not
produce a bad frame.
• Y—Yes. Changing the register value might produce a
bad frame.
• YM—Yes; but the bad frame is masked out unless
the “show bad frames” feature (Reg0x0D[8]) is
enabled.
Changes to Integration Time
If the integration time (Reg0x09) is changed while
FRAME_VALID is asserted for frame n, the first frame
output using the new integration time is frame (n+2).
The sequence is as follows:
1. During frame n, the new integration time is held
in the Reg0x09 pending register.
2. At the start of frame (n+1), the new integration
time is transferred to the Reg0x09 live register.
Integration for each row of frame (n+1) has been
completed using the old integration time. The earliest
time that a row can start integrating using the new
integration time is immediately after that row has been
read for frame (n+1). The actual time that rows start
integrating using the new integration time is depen-
dent on the new value of the integration time.
3. When frame (n+1) is read out, it is integrated
using the new integration time.
If the integration time is changed (Reg0x09 written)
on successive frames, each value written is applied to a
single frame; the latency between writing a value and it
affecting the frame readout remains at two frames.
Changes to Gain Settings
When
the
gain
settings
(Reg0x2B,
Reg0x2C,
Reg0x2D, Reg0x2E, and Reg0x2F) are changed, the gain
is usually updated on the next frame start. When the
integration time and the gain are changed simulta-
neously, the gain update is held off by one frame so
that the first frame output with the new integration
time also has the new gain applied.



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