MT9D011 datasheet(13/61 Pages) MICRON

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MT9D011

2-MEGAPIXEL DIGITAL IMAGE SENSOR

PRELIMINARY

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN

Two-Wire Serial Register Interface

This section describes the two-wire serial interface

bus that can be used in any functional sensor mode.

The two-wire serial interface bus enables R/W

access to control and status registers within the

MT9D011.

The interface protocol uses a master/slave model in

which a master controls one or more slave devices. The

sensor acts as a slave device. The master generates a

clock (SCLK) that is an input to the sensor and used to

synchronize transfers. The master is responsible for

driving a valid logic level on SCLK at all times. Data is

transferred between the master and the slave on a bi-

directional signal (SDATA). The SDATA signal is pulled

up to VDD off-chip by a 1.5k

Ω resistor. Either the slave

or master device can drive the SDATA line low—the

interface protocol determines which device is allowed

to drive the SDATA line at any given time.

Protocol

The two-wire serial interface bus defines the trans-

mission codes as follows:

•a start bit

• the slave device 8-bit address

• a(an) (no) acknowledge bit

• an 8-bit message

•a stop bit

Sequence

A typical read or write sequence is executed as fol-

lows:

1. The master sends a start bit.

2. The master sends the 8-bit slave device address.

The last bit of the address determines if the

request is a read or a write, where a “0” indicates a

write and a “1” indicates a read.

3. The slave device acknowledges receipt of the

address by sending an acknowledge bit to the

master.

4. If the request is a write, the master then transfers

the 8-bit register address, indicating where the

write takes place.

5. The slave sends an acknowledge bit, indicating

that the register address has been received.

6. The master then transfers the data, eight bits at a

time, with the slave sending an acknowledge bit

after each eight bits.

The MT9D011 uses 16-bit data for its internal regis-

ters, thus requiring two 8-bit transfers to write to one

address is automatically incremented so that the next

16 bits are written to the next register address. The

master stops writing by sending a start or stop bit.

A typical read sequence is executed as follows.

1. The master sends the write-mode slave address

and 8-bit register address, just as in the write

request.

2. The master then sends a start bit and the read-

mode slave address, and clocks out the register

data, eight bits at a time.

3. The master sends an acknowledge bit after each

8-bit transfer. The register address is auto-incre-

mented after every 16 bits is transferred.

4. The data transfer is stopped when the master

sends a no-acknowledge bit.

Bus Idle State

The bus is idle when both the data and clock lines

are high. Control of the bus is initiated with a start bit,

and the bus is released with a stop bit. Only the master

can generate start and stop bits.

Start Bit

The start bit is defined as a HIGH-to-LOW data line

transition while the clock line is HIGH.

Stop Bit

The stop bit is defined as a lLOW-to-HIGH data line

transition while the clock line is HIGH.

Slave Address

The 8-bit address of a two-wire serial interface

device consists of seven bits of address and one bit of

direction. A “0” in the LSB (least significant bit) of the

address indicates write mode, and a “1” indicates read

mode. The default slave addresses used by the

MT9D011 are 0xBA (write address) and 0xBB (read

address). Reg0x0D[10] or the SADDR pin can be used to

select the alternate slave addresses 0x90 (write

address) and 0x91 (read address).

Writes to Reg0x0D[10] are inhibited when the

standby pin is asserted (all other writes proceed nor-

mally). This allows two sensors to co-exist as slaves on

this interface, but they must be addressed indepen-

dently. Enable this capability as follows:

MT9D011 Datasheet(PDF) 13 Page - Micron Technology

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