AD7656ABSTZ datasheet(16/29 Pages) AD

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Data Sheet

AD7656A

THEORY OF OPERATION

CONVERTER DETAILS

The AD7656A is a high speed, low power converter that allows

the simultaneous sampling of six on-chip analog-to-digital

converts (ADCs). The analog inputs on the AD7656A can

accept true bipolar input signals. The RANGE pin/RNGx bits

are used to select either ±4 × VREF or ±2 × VREF as the input

range for the next conversion.

The AD7656A contains six successive approximation (SAR)

ADCs, six track-and-hold amplifiers, an on-chip 2.5 V reference,

reference buffers, and high speed parallel and serial interfaces.

The AD7656A allows the simultaneous sampling of all six ADCs

when the three CONVST x pins (CONVST A, CONVST B, and

CONVST C) are tied together. Alternatively, the six ADCs can be

grouped into three pairs. Each pair has an associated CONVST

signal used to initiate simultaneous sampling on each ADC pair,

on four ADCs, or on all six ADCs. CONVST A is used to initiate

simultaneous sampling on V1 and V2, CONVST B is used to

initiate simultaneous sampling on V3 and V4, and CONVST C

is used to initiate simultaneous sampling on V5 and V6.

A conversion is initiated on the AD7656A by pulsing the

CONVST x input. On the rising edge of CONVST x, the track-

and-hold amplifier of the selected ADC pair is placed into hold

mode and the conversions are started. After the rising edge of

CONVST x, the BUSY signal goes high to indicate that the

conversion is taking place. The conversion clock for the

AD7656A is internally generated, and the conversion time for

the device is 3 µs. The BUSY signal returns low to indicate the

end of conversion. On the falling edge of BUSY, the track-and-

hold amplifier returns to track mode. Data can be read from the

output register via the parallel or serial interface.

Track-and-Hold Amplifiers

The track-and-hold amplifiers on the AD7656A allow the ADCs

to accurately convert an input sine wave of full-scale amplitude

to 16-bit resolution. The input bandwidth of the track-and-hold

amplifiers is greater than the Nyquist rate of the ADC, even

when the AD7656A is operating at its maximum throughput

rate. The device can handle input frequencies of up to 12 MHz.

The track-and-hold amplifiers sample their respective inputs

simultaneously on the rising edge of CONVST x. The aperture time

(that is, the delay time between the external CONVST x signal

actually entering hold) for the track-and-hold is 10 ns. This is well

matched across all six track-and-hold amplifiers on one device and

from device to device. This allows more than six ADCs to be

sampled simultaneously. The end of the conversion is signaled by

the falling edge of BUSY, and it is at this point that the track-and-

hold amplifiers return to track mode and the acquisition time

begins.

Analog Input

The AD7656A can handle true bipolar input voltages. The logic

level on the RANGE pin or the value written to the RNGx bits

in the control register determines the analog input range on the

AD7656A for the next conversion. When the RANGE pin or

RNGx bit is 1, the analog input range for the next conversion is

±2 × VREF. When the RANGE pin or RNGx bit is 0, the analog

input range for the next conversion is ±4 × VREF.

VDD

VDD_INTERNAL

VSS

VSS_INTERNAL

Figure 20. Equivalent Analog Input Structure

Figure 20 shows an equivalent circuit of the analog input of

structure of the AD7656A. The two diodes, D1 and D2, provide

ESD protection for the analog inputs. Care must be taken to

ensure that the analog input signal never exceeds the VDD and

VSS supply rail limits by more than VSS + 1 V and VDD − 1 V.

Signals exceeding this value cause these diode to become forward-

biased and to start conducting into the substrate. The maximum

current these diodes can conduct without causing irreversible

damage to the device is 10 mA. Capacitor C1 in Figure 20 is

typically about 4 pF and can be attributed primarily to pin

capacitance. Resistor R1 is a lumped component made up of the

on resistance of a switch (that is, track-and-hold switch). This

resistor is typically about 25 Ω. Capacitor C2 is the ADC

sampling capacitor and has a capacitance of 10 pF typically.

The AD7656A requires VDD and VSS dual supplies for the high

voltage analog input structures. These supplies must be greater

than the analog input range (see Table 6 for the requirements on

these supplies for each analog input range). The AD7656A

requires a low voltage AVCC supply of 4.75 V to 5.25 V to power

the ADC core, a DVCC supply of 4.75 V to 5.25 V for the digital

power, and a VDRIVE supply of 2.7 V to 5.25 V for the interface

power.

To meet the specified performance when using the minimum

supply voltage for the selected analog input range, it may be

necessary to reduce the throughput rate from the maximum

throughput rate.

Table 6. Minimum VDD/VSS Supply Voltage Requirements

Analog Input

Range (V)

Reference

Voltage (V)

Full-Scale

Input (V)

Minimum

VDD/VSS (V)

±4 × VREF

2.5

±10

±11

±4 × VREF

3.0

±12

±13

±2 × VREF

2.5

±5

±6

±2 × VREF

3.0

±6

±7

Rev. 0 | Page 15 of 28

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