Electronic Components Datasheet Search
  English  ▼

X  

AD7656ABSTZ Datasheet(PDF) 22 Page - Analog Devices

Part # AD7656ABSTZ
Description  250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-Bit ADC
PDF  29 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7656ABSTZ Datasheet(HTML) 22 Page - Analog Devices

Back Button AD7656ABSTZ Datasheet HTML 18Page - Analog Devices AD7656ABSTZ Datasheet HTML 19Page - Analog Devices AD7656ABSTZ Datasheet HTML 20Page - Analog Devices AD7656ABSTZ Datasheet HTML 21Page - Analog Devices AD7656ABSTZ Datasheet HTML 22Page - Analog Devices AD7656ABSTZ Datasheet HTML 23Page - Analog Devices AD7656ABSTZ Datasheet HTML 24Page - Analog Devices AD7656ABSTZ Datasheet HTML 25Page - Analog Devices AD7656ABSTZ Datasheet HTML 26Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 29 page
background image
Data Sheet
AD7656A
V1
V2
V5
DOUT A
DOUT B
48
V3
V4
V6
SCLK
CS
Figure 27. Serial Interface with Two DOUT x Lines
BUSY
ACQUISITION
CONVERSION
ACQUISITION
SCLK
CS
DOUT A,
DOUT B,
DOUT C
DB15
DB14
DB13
DB1
DB0
tACQ
t10
tCONVERT
t2
t1
tQUIET
t21
t20
t17
t16
t18
t19
CONVST A,
CONVST B,
CONVST C
Figure 28. Serial Read Operation
DIGITAL HOST
CONVERT
CS
SCLK
AD7656A
AD7656A
CONVST x
CONVST x
CS
CS
SCLK
SCLK
DATA IN1
DATA IN2
DOUT A
DOUT B
DOUT A
DOUT B
DCIN A
DCIN B
DCEN = 1
DEVICE 1
DCEN = 0
DEVICE 2
Figure 29. Daisy-Chain Configuration
SERIAL READ OPERATION
Figure 28 shows the timing diagram for reading data from the
AD7656A serial interface. The SCLK input signal provides the
clock source for the serial interface. The CS signal goes low to
access data from the AD7656A. The falling edge of CS takes
the bus out of a three-state condition and clocks out the MSB of
the 16-bit conversion result. The ADCs output 16 bits for each
conversion result; the data stream of the AD7656A consists of
16 bits of conversion data provided MSB first.
The first bit of the conversion result is valid on the first SCLK
falling edge after the CS falling edge. The subsequent 15 data
bits are clocked out on the rising edge of the SCLK signal. Data
is valid on the SCLK falling edge. To access each conversion result,
provide 16 clock pulses to the AD7656A. Figure 28 shows how a
16-SCLK read is used to access the conversion results.
DAISY-CHAIN MODE (DCEN = 1, SER/PAR/SEL = 1)
When reading conversion data back from the AD7656A using
their three, two, and one DOUT x pins, it is possible to configure
the device to operate in daisy-chain mode using the DCEN pin.
This daisy-chain feature allows multiple AD7656A devices to be
cascaded together and is useful for reducing the component
count and wiring connections. An example connection of two
devices is shown in Figure 29. This configuration shows the use
of two DOUT x lines. Simultaneous sampling of the 12 analog
inputs is possible by using a common CONVST x signal. The
DB5, DB4, and DB3 pins are used as the DCIN A to DCIN C data
input pins for the daisy-chain mode.
Rev. 0 | Page 21 of 28



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com