AD7656ABSTZ datasheet(25/29 Pages) AD

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AD7656A

Data Sheet

APPLICATION HINTS

LAYOUT

Design the printed circuit board (PCB) that houses the AD7656A

so that the analog and digital sections are separated and confined

to different areas of the board.

Use at least one ground plane. The ground plane can be common

or split between the digital and analog sections. In the case of

the split plane, join the digital and analog ground planes in only

one place, preferably underneath the AD7656A, or at least as

close as possible to the device.

If the AD7656A is in a system where multiple devices require

analog-to-digital ground connections, still make the connection

at only one point, a star ground point, and established it as close

as possible to the AD7656A. Make good connections to the

ground plane. Avoid sharing one connection for multiple

ground pins. Use individual vias or multiple vias to the ground

plane for each ground pin.

Avoid running digital lines under the device because doing so

couples noise onto the die. Allow the analog ground plane to

run under the AD7656A to avoid noise coupling. Shield fast

switching signals, like CONVST x or clocks, with digital ground

to avoid radiating noise to other sections of the board, and

ensure that they never run near the analog signal paths. Avoid

crossover of digital and analog signals. Run traces in close

proximity on the board at right angles to each other to reduce

the effect of feedthrough through the board.

For the power supply lines to the AVCC, DVCC, VDRIVE, VDD, and

VSS pins on the AD7656A use as large a trace as possible to

provide low impedance paths and to reduce the effect of glitches

on the power supply lines. Establish good connections between

the AD7656A supply pins and the power tracks on the board;

involve the use of a single via or multiple vias for each supply

pin.

Good decoupling is also important to lower the supply impedance

presented to the AD7656A and to reduce the magnitude of the

supply spikes. Place decoupling ceramic capacitors, typically

100 nF, on all of the power supply pins, VDD, VSS, AVCC, DVCC,

and VDRIVE. Place these decoupling capacitors close to, but

ideally right up against, these pins and their corresponding

ground pins. Additionally, place low ESR 10 µF capacitors on

each of the supply pins. Avoid sharing these capacitors between

pins. Use big vias to connect the capacitors to the power and

ground planes. Use wide, short traces between the via and the

capacitor pad, or place the via adjacent to the capacitor pad to

minimize parasitic inductances. Recommended decoupling

capacitors are 100 nF, low ESR, ceramic capacitors and 10 µF, low

ESR, tantalum capacitors for the AVCC decoupling. Place a large

tantalum decoupling capacitor where the AVCC supply enters

the board.

An alternative reduced decoupling arrangement is outlined in

the Typical Connection Diagram section. This decoupling

arrangement groups the AVCC supply pins into pairs and allows

the decoupling capacitors to be shared between the supply pairs.

Group the six AVCC core supply pins into three pairs, Pin 34 and

Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47. Connect the

supply pins in each pair together; their location on the AD7656A

pin configuration easily facilitates this. For the AD7656A, decouple

each pair with a 100 µF capacitor. For this minimum decoupling

configuration, decouple all other supply and reference pins with

a 10 µF decoupling capacitor.

Rev. 0 | Page 24 of 28

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