AD7656ABSTZ datasheet(23/29 Pages) AD

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AD7656A

Data Sheet

The rising edge of CONVST x is used to initiate a conversion on

the AD7656A. After the BUSY signal has gone low to indicate

that the conversion is complete, the user can begin to read the data

from the two devices. Figure 30 shows the serial timing diagram

when operating two AD7656A devices in daisy-chain mode.

The CS falling edge is used to frame the serial transfer from the

AD7656A to take the bus out of three-state and to clock out the

MSB of the first conversion result. In the example shown in

Figure 30, all 12 ADC channels are simultaneously sampled. Two

DOUT x lines are used to read the conversion results in this

example. CS frames a 96-SCLK transfer. During the first 48 SCLKs,

the conversion data is transferred from Device 2 to Device 1.

DOUT A on Device 2 transfers conversion data from V1, V2,

and V5 into DCIN A in Device 1. DOUT B on Device 2 transfers

conversion results from V3, V4, and V6 to DCIN B in Device 1.

During the first 48 SCLKs, Device 1 transfers data into the digital

host. DOUT A on Device 1 transfers conversion data from V1,

V2, and V5. DOUT B on Device 1 transfers conversion data from

V3, V4, and V6. During the last 48-SCLKs, Device 2 clocks out

zeros and Device 1 shifts the data clocked in from Device 2 during

the first 48 SCLKs into the digital host. This example can also

be implemented using six 16-SCLK individually framed transfers if

DCEN remains high during the transfers.

Figure 31 shows the timing if two AD7656A devices are configured

in daisy-chain mode and are operating with three DOUT x

lines. Assuming a simultaneous sampling of all 12 inputs

occurs, the CS frames a 64-SCLK transfer during the read

operation. During the first 32 SCLKs of this transfer, the

conversion results from Device 1 are clocked into the digital

host, and the conversion results from Device 2 are clocked into

Device 1. During the last 32 SCLKs of the transfer, the

conversion results from Device 2 are clocked out of Device 1

and into the digital host. Device 2 clocks out zeros.

DEVICE 1, DOUT A

MSB V1

LSB V1

MSB V2

LSB V2

MSB V5

LSB V5

MSB V1

LSB V1

MSB V2

LSB V5

MSB V1

LSB V1

MSB V2

LSB V2

MSB V5

LSB V5

BUSY

SCLK

DEVICE 1, DOUT B

MSB V3

LSB V3

MSB V4

LSB V4

MSB V6

LSB V6

MSB V3

LSB V3

MSB V4

LSB V6

DEVICE 2, DOUT A

MSB V3

LSB V3

MSB V4

LSB V4

MSB V6

LSB V6

DEVICE 2, DOUT B

CONVST A,

CONVST B,

CONVST C

Figure 30. Daisy-Chain Serial Interface Timing with Two DOUT x Lines

DEVICE 1, DOUT A

MSB V1

LSB V1

MSB V2

LSB V2

MSB V1

LSB V1

MSB V2

LSB V2

MSB V1

LSB V1

MSB V2

LSB V2

BUSY

SCLK

DEVICE 2, DOUT A

MSB V3

LSB V3

MSB V4

LSB V4

DEVICE 2, DOUT B

DEVICE 1, DOUT B

MSB V3

LSB V3

MSB V4

LSB V4

MSB V3

LSB V3

MSB V4

LSB V4

DEVICE 1, DOUT C

MSB V5

LSB V5

MSB V6

LSB V6

MSB V5

LSB V5

MSB V6

LSB V6

MSB V5

LSB V5

MSB V6

LSB V6

DEVICE 2, DOUT C

CONVST A,

CONVST B,

CONVST C

Figure 31. Daisy-Chain Serial Interface Timing with Three DOUT x Lines

Rev. 0 | Page 22 of 28

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