TMS44100, TMS44100P, TMS46100, TMS46100P

4194304-WORD BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS561A – MARCH 1995 – REVISED JUNE 1995

14

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

Don’t Care

Don’t Care

RAS

CAS

A0 – A10

W

Q

D

tRWC

Row

Column

Don’t Care

tRAS

tRCD

tT

tCAS

tRP

tCRP

tCP

tCAH

tASC

tRAH

tRCS

tAWD

tRWL

tWP

tAR

tCWL

Valid In

Valid Out

tDS

tCWD

tRWD

tOFF

tDH

tCLZ

tCAC

tAA

tRAC

(see Note A)

Hi-Z

tASR

tRAD

tCAH

Don’t Care

Don’t Care

NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

Figure 6. Read-Write-Cycle Timing