TMS44100, TMS44100P, TMS46100, TMS46100P

4194304-WORD BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS561A – MARCH 1995 – REVISED JUNE 1995

16

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0 – A10

W

Q

D

Row

Column

Don’t Care

See Note A

See Note A

Valid

Data In

tRP

Valid Data In

Don’t Care

Hi-Z

Don’t Care

Don’t Care

Don’t Care

Column

tRASP

tCSH

tPC

tCRP

tRSH

tCAS

tRCD

tASC

tRAH

tCAH

tCP

tASR

tRAD

tCWL

tWP

tCWL

tRWL

tDH

tDH

(see Note A)

tDS

tDS

tRAL

tAR

tDHR

tWCR

See Note A

tCAL

NOTES: A. Referenced to CAS or W, whichever occurs last

B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not

violated.

Figure 8. Enhanced-Page-Mode Write-Cycle Timing