T0516ST datasheet(4/7 Pages) CITC

4 / 7 page

Application Information

Pin Connection in PCB

and one power rail line simultaneously. The pin

connection is shown in Figure 1.

Six parallel data lines, from inner IC to I/O port

connector, could connect to T0516ST six I/O pins

directly. Pin 9 of T0516ST is the GND pin, which

should connect to the GND of PCB. The wire should

be as short as possible in order to minimize the

parasitic inductance. Pin 2 of T0516ST is the VCC

pin, which should connect to the VCC rail of PCB.

In some cases, systems are not allowed to be reset or

restart after zapping ESD stress at the I/O port connector

Under this situation, to enhance the sustainable ESD

level, a 0.1uF capacitor can be used berween the VCC

and GND rails. Place the capacitor as close as possible

to T0516ST.

In some cases, VCC rail is not presented on the PCB.

Under this situation, the pin 2 of T0516ST can be left

as ﬂoating. The pin connection is show

I/O1

I/O2

GND

VCC

To Connector

I/O4

I/O5

To Inner IC

I/O3

I/O6

To Inner IC

To Connector

0.1 F

Figure 1

T0516ST pin connection in PCB providing data lines

and power rail line protection.

I/O1

I/O2

GND

VCC ﬂoated

To Connector

I/O4

I/O5

To Inner IC

I/O3

I/O6

To Inner IC

To Connector

Figure 2 T0516ST pin connection in PCB providing data line protection.

VCC pin is left as ﬂoating when no VCC rail is presented in PCB

T0516ST provides ESD protection for six data lines

T0516ST

Chip Integration Technology Corporation

Document ID : DS-22V08

Revised Date : 2016/08/29

Revision : C

Ultra-Low Capacitance ESD Protection Device

T0516ST Datasheet(PDF) 4 Page - Chip Integration Technology Corporation

T0516ST Datasheet(HTML) 4 Page - Chip Integration Technology Corporation

Html Pages

1 2 3 4 5 6 7

Datasheet Download

Link URL