AD9254 datasheet(19/41 Pages) AD

19 / 41 page

AD9254

Rev. 0 | Page 18 of 40

0.1µF

SCHOTTKY

DIODES:

HMS2812

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

AD9254

MINI-CIRCUITS

ADT1–1WT, 1:1Z

XFMR

Figure 41. Transformer Coupled Differential Clock

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins as shown in Figure 42. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515 family of clock drivers offers

excellent jitter performance.

100Ω

0.1µF

240Ω

AD951x

PECL DRIVER

50Ω1

CLK

150Ω RESISTORS ARE OPTIONAL.

CLK–

CLK+

ADC

AD9254

CLOCK

INPUT

CLOCK

INPUT

Figure 42. Differential PECL Sample Clock

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 43. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515 family of clock

drivers offers excellent jitter performance.

100Ω

0.1µF

50Ω1

AD951x

LVDS DRIVER

50Ω1

CLK

150Ω RESISTORS ARE OPTIONAL.

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

ADC

AD9254

Figure 43. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

directly drive CLK+ from a CMOS gate, while bypassing the

CLK− pin to ground using a 0.1 μF capacitor in parallel with a

39 kΩ resistor (see Figure 44). CLK+ can be directly driven

from a CMOS gate. This input is designed to withstand input

voltages up to 3.6 V, making the selection of the drive logic

voltage very flexible. When driving CLK+ with a 1.8 V CMOS

signal, biasing the CLK− pin with a 0.1 μF capacitor in parallel

with a 39 kΩ resistor (see Figure 44) is required. The 39 kΩ

resistor is not required when driving CLK+ with a 3.3 V CMOS

signal (see Figure 45).

OPTIONAL

100Ω

0.1µF

39kΩ

AD951x

CMOS DRIVER

50Ω1

150Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD9254

VCC

1kΩ

CLOCK

INPUT

Figure 44. Single-Ended 1.8 V CMOS Sample Clock

150Ω RESISTOR IS OPTIONAL.

OPTIONAL

100Ω

0.1µF

VCC

AD951x

CMOS DRIVER

50Ω1

CLK–

CLK+

ADC

AD9254

1kΩ

CLOCK

INPUT

Figure 45. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. Commonly, a ±5% tolerance is

required on the clock duty cycle to maintain dynamic

performance characteristics.

The AD9254 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling, or falling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9254. Noise and distortion performance are nearly flat

for a wide range of duty cycles when the DCS is on, as shown in

Figure 28.

Jitter in the rising edge of the input is still of paramount concern

and is not reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates less than

20 MHz nominally. The loop has a time constant associated

with it that needs to be considered in applications where the

clock rate can change dynamically. This requires a wait time

of 1.5 μs to 5 μs after a dynamic clock frequency increase (or

decrease) before the DCS loop is relocked to the input signal.

During the time period the loop is not locked, the DCS loop is

bypassed, and the internal device timing is dependent on the

duty cycle of the input clock signal. In such an application, it

may be appropriate to disable the duty cycle stabilizer. In all

other applications, enabling the DCS circuit is recommended

to maximize ac performance.

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