AD9254 datasheet(21/41 Pages) AD

21 / 41 page

AD9254

Rev. 0 | Page 20 of 40

Standby Mode

When using the SPI port interface, the user can place the ADC

in power-down or standby modes. Standby mode allows the

user to keep the internal reference circuitry powered when

faster wake-up times are required (see the Memory Map section).

DIGITAL OUTPUTS

The AD9254 output drivers can be configured to interface with

1.8 V to 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic. The output drivers are sized to

provide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fan-outs may require external buffers or latches.

The output data format can be selected for either offset binary

or twos complement by setting the SCLK/DFS pin when operat-

ing in the external pin mode (see Table 10). As detailed in the

Interfacing to High Speed ADCs via SPI user manual, the data

format can be selected for either offset binary, twos complement,

or Gray code when using the SPI control.

Out-of-Range (OR) Condition

An out-of-range condition exists when the analog input voltage

is beyond the input range of the ADC. OR is a digital output

that is updated along with the data output corresponding to the

particular sampled input voltage. Thus, OR has the same

pipeline latency as the digital data.

OR DATA OUTPUTS

+FS – 1 LSB

+FS – 1/2 LSB

+FS

–FS

–FS + 1/2 LSB

–FS – 1/2 LSB

1111

1110

0000

0001

0000

Figure 48. OR Relation to Input Voltage and Output Data

OR is low when the analog input voltage is within the analog

input range and high when the analog input voltage exceeds the

input range, as shown in Figure 48. OR remains high until the

analog input returns to within the input range and another

conversion is completed.

By logically AND’ing the OR bit with the MSB and its complement,

overrange high or underrange low conditions can be detected.

Table 11 is a truth table for the overrange/underrange circuit in

Figure 49, which uses NAND gates.

MSB

OVER = 1

UNDER = 1

Figure 49. Overrange/Underrange Logic

Table 11. Overrange/Underrange Truth Table

MSB

Analog Input Is:

Within range

Underrange

Overrange

Digital Output Enable Function (OEB)

The AD9254 has three-state ability. If the OEB pin is low, the

output data drivers are enabled. If the OEB pin is high, the

output data drivers are placed in a high impedance state. This is

not intended for rapid access to the data bus. Note that OEB is

referenced to the digital supplies (DRVDD) and should not

exceed that supply voltage.

TIMING

The lowest typical conversion rate of the AD9254 is 10 MSPS.

At clock rates below 10 MSPS, dynamic performance can degrade.

The AD9254 provides latched data outputs with a pipeline delay

of twelve clock cycles. Data outputs are available one propaga-

tion delay (tPD) after the rising edge of the clock signal.

The length of the output data lines and the loads placed on

them should be minimized to reduce transients within the

AD9254. These transients can degrade the dynamic performance

of the converter.

Data Clock Output (DCO)

The AD9254 also provides data clock output (DCO) intended for

capturing the data in an external register. The data outputs are valid

on the rising edge of DCO, unless the DCO clock polarity has been

changed via the SPI. See Figure 2 for a graphical timing

description.

Table 12. Output Data Format

Input (V)

Condition (V)

Binary Output Mode

Twos Complement Mode

Gray Code Mode

(SPI Accessible)

VIN+ – VIN–

< –VREF – 0.5 LSB

00 0000 0000 0000

10 0000 0000 0000

11 0000 0000 0000

VIN+ – VIN–

= –VREF

00 0000 0000 0000

10 0000 0000 0000

11 0000 0000 0000

VIN+ – VIN–

= 0

10 0000 0000 0000

00 0000 0000 0000

VIN+ – VIN–

= +VREF – 1.0 LSB

11 1111 1111 1111

01 1111 1111 1111

10 0000 0000 0000

VIN+ – VIN–

> +VREF – 0.5 LSB

11 1111 1111 1111

01 1111 1111 1111

10 0000 0000 0000

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