AD9601 datasheet(23/33 Pages) AD

23 / 33 page

AD9601

Rev. 0 | Page 22 of 32

Table 10. Serial Timing Definitions

Parameter

Timing (minimum, ns)

Description

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHI

Minimum period that SCLK should be in a logic high state

tLO

Minimum period that SCLK should be in a logic low state

tEN_SDIO

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 44)

tDIS_SDIO

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge (not shown in Figure 44)

Table 11. Output Data Format

Input (V)

Condition (V)

Offset Binary Output Mode

D11 to D0

Twos Complement Mode

D11 to D0

Gray Code Mode

(SPI Accessible)

D11 to D0

VIN+ − VIN−

< 0.62

0000 0000 0000

VIN+ − VIN−

= 0.62

0000 0000 0000

VIN+ − VIN−

= 0

0000 0000 0000

VIN+ − VIN−

= 0.62

1111 1111 1111

0000 0000 0000

VIN+ − VIN−

> 0.62 + 0.5 LSB

1111 1111 1111

0000 0000 0000

AD9601 Datasheet(PDF) 23 Page - Analog Devices

AD9601 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL