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AD9626

Rev. 0 | Page 18 of 36

THEORY OF OPERATION

The AD9626 architecture consists of a front-end sample-and-

hold amplifier (SHA) followed by a pipelined switched capacitor

ADC. The quantized outputs from each stage are combined into

a final 12-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate on a new input

sample, while the remaining stages operate on preceding

samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be ac- or

dc-coupled. The output-staging block aligns the data, carries

out the error correction, and passes the data to the output

buffers. The output buffers are powered from a separate supply,

allowing adjustment of the output voltage swing. During power-

down, the output buffers go into a high impedance state.

ANALOG INPUT AND VOLTAGE REFERENCE

The analog input to the AD9626 is a differential buffer. For best

dynamic performance, the source impedances driving VIN+

and VIN− should be matched such that common-mode settling

errors are symmetrical. The analog input is optimized to

provide superior wideband performance and requires that the

analog inputs be driven differentially.

A wideband transformer, such as Mini-Circuits® ADT1-1WT,

can provide the differential analog inputs for applications that

require a single-ended-to-differential conversion. Both analog

inputs are self-biased by an on-chip resistor divider to a

nominal 1.4 V.

An internal differential voltage reference creates positive and

negative reference voltages that define the 1.25 V p-p fixed span

of the ADC core. This internal voltage reference can be adjusted

by means of SPI control. See the AD9626 Configuration Using

the SPI section for more details.

Differential Input Configurations

Optimum performance is achieved while driving the AD9626

in a differential input configuration. For baseband applications,

the AD8138 differential driver provides excellent performance

and a flexible interface to the ADC. The output common-mode

voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

VIN+

VIN–

AVDD

CML

AD8138

523Ω

499Ω

33Ω

49.9Ω

1V p-p

0.1µF

20pF

AD9626

Figure 42. Differential Input Configuration Using the AD8138

At input frequencies in the second Nyquist zone and above, the

performance of most amplifiers may not be adequate to achieve

the true performance of the AD9626. This is especially true in

IF undersampling applications where frequencies in the 70 MHz

to 100 MHz range are being sampled. For these applications,

differential transformer coupling is the recommended input

configuration. The signal characteristics must be considered

when selecting a transformer. Most RF transformers saturate at

frequencies below a few millihertz, and excessive signal power

can also cause core saturation, which leads to distortion.

In any configuration, the value of the shunt capacitor, C, is

dependent on the input frequency and may need to be reduced

or removed.

VIN+

VIN–

15Ω

50Ω

1.25V p-p

0.1µF

2pF

AD9626

Figure 43. Differential Transformer-Coupled Configuration

As an alternative to using a transformer-coupled input at

frequencies in the second Nyquist zone, the AD8352 differential

driver can be used (see Figure 44).

AD9626

AD8352

0Ω

0.1µF

VIN+

VIN– CML

0.1µF

8, 13

VCC

200Ω

ANALOG INPUT

Figure 44. Differential Input Configuration Using the AD8352

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