AD9446 datasheet(7/37 Pages) AD

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AD9446

Rev. 0 | Page 6 of 36

DIGITAL SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.

Table 3.

AD9446BSVZ-80

AD9446BSVZ-100

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Unit

CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)

High Level Input Voltage

Full

2.0

Low Level Input Voltage

Full

0.8

High Level Input Current

Full

200

μA

Low Level Input Current

Full

−10

+10

−10

+10

μA

Input Capacitance

Full

DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)1

DRVDD = 3.3 V

High Level Output Voltage

Full

3.25

Low Level Output Voltage

Full

0.2

DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)

VOD Differential Output Voltage2

Full

247

545

247

545

VOS Output Offset Voltage

Full

1.125

1.375

1.125

1.375

CLOCK INPUTS (CLK+, CLK−)

Differential Input Voltage

Full

0.2

Common-Mode Voltage

Full

1.3

1.5

1.6

1.3

1.5

1.6

Input Resistance

Full

1.1

1.4

1.7

1.1

1.4

1.7

kΩ

Input Capacitance

Full

1 Output voltage levels measured with 5 pF load on each output.

2 LVDS RTERM = 100 Ω.

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4.

AD9446BSVZ-80

AD9446BSVZ-100

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate

Full

100

MSPS

Minimum Conversion Rate

Full

MSPS

CLK Period

Full

12.5

CLK Pulse Width High1 (tCLKH)

Full

5.0

4.0

CLK Pulse Width Low1 (tCLKL)

Full

5.0

4.0

DATA OUTPUT PARAMETERS

Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+)

Full

3.35

Output Propagation Delay—LVDS (tPD)3 (Dx+), (tCPD)3 (DCO+)

Full

2.1

3.6

4.8

2.3

3.6

4.8

Pipeline Delay (Latency)

Full

Cycles

Aperture Delay (tA)

Full

Aperture Uncertainty (Jitter, tJ)

Full

fsec

rms

1 With duty cycle stabilizer (DCS) enabled.

2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.

3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

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