AD9446 datasheet(29/37 Pages) AD

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AD9446

Rev. 0 | Page 28 of 36

OPERATIONAL MODE SELECTION

Data Format Select

The data format select (DFS) pin of the AD9446 determines

the coding format of the output data. This pin is 3.3 V CMOS

compatible, with logic high (or AVDD1, 3.3 V) selecting twos

complement and DFS logic low (AGND) selecting offset binary

format. Table 10 summarizes the output coding.

Output Mode Select

The OUPUT MODE pin controls the logic compatibility,

as well as the pinout of the digital outputs. This pin is a CMOS-

compatible input. With OUTPUT MODE = 0 (AGND), the

AD9446 outputs are CMOS compatible, and the pin assignment

for the device is as defined in Table 8. With OUTPUT MODE = 1

(AVDD1, 3.3 V), the AD9446 outputs are LVDS compatible, and

the pin assignment for the device is as defined in Table 7.

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS MODE pin; a CMOS

logic low (AGND) on DCS MODE enables the DCS, and logic

high (AVDD1, 3.3 V) disables the controller.

Table 10. Digital Output Coding

Code

VIN+ − VIN−

Input Span = 3.2 V p-p (V)

VIN+ − VIN−

Input Span = 2 V p-p (V)

Digital Output

Offset Binary (D15••••••D0)

Digital Output

Twos Complement (D15••••••D0)

65,536

+1.600

+1.000

1111 1111 1111 1111

0111 1111 1111 1111

32,768

1000 0000 0000 0000

0000 0000 0000 0000

32,767

−0.0000488

−0.000122

0111 1111 1111 1111

1111 1111 1111 1111

−1.60

−1.00

0000 0000 0000 0000

1000 0000 0000 0000

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