AD9481 datasheet(7/29 Pages) AD

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AD9481

Rev. 0 | Page 6 of 28

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted.

Table 4.

AD9481-250

Parameter

Temp

Test Level

Min

Typ

Max

Unit

CLOCK

Maximum Conversion Rate

Full

250

MSPS

Minimum Conversion Rate

Full

MSPS

Clock Pulse-Width High (tEH)

Full

1.2

Clock Pulse-Width Low (tEL)

Full

1.2

DS Input Setup Time (tSDS)

Full

0.5

DS Input Hold Time (tHDS)

Full

0.5

OUTPUT PARAMETERS1

Valid Time (tV)2

Full

2.5

Propagation Delay (tPD)

Full

5.4

Rise Time (tR) 10% to 90%

Full

670

Fall Time (tF) 10% to 90%

Full

360

DCO Propagation Delay (tCPD) 3

Full

2.5

3.9

5.3

Data-to-DCO Skew (tPD − tCPD)4

Full

−0.5

+0.5

A Port Data to DCO− Rising (tSKA)5

Full

B Port Data to DCO+ Rising (tSKB)

Full

Pipeline Latency (A, B)

Full

Cycles

APERTURE

Aperture Delay (tA)

25°C

1.5

Aperture Uncertainty (Jitter)

25°C

0.25

ps rms

OUT-OF-RANGE RECOVERY TIME

25°C

Cycle

1 CLOAD equals 5 pF maximum for all output switching specifications.

2 Valid time is approximately equal to minimum tPD.

3 TCPD equals clock rising edge to DCO (+ or −) rising edge delay.

4 Data changing to (DCO+ or DCO−) rising edge delay.

5 TSKA, TSKB are both clock rate dependent delays equal to TCYCLE − (Data to DCO skew).

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