AD9214 datasheet(13/21 Pages) AD

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REV. D

AD9214

–12–

THEORY OF OPERATION

The AD9214 architecture is a bit-per-stage pipeline converter

utilizing switch capacitor techniques. These stages determine

the 7 MSBs and drive a 3-bit flash. Each stage provides suffi-

cient overlap and error correction allowing optimization of

comparator accuracy. The input buffer is differential and both

inputs are internally biased. This allows the most flexible use of

ac or dc and differential or single-ended input modes. The out-

put staging block aligns the data, carries out the error correction

and feeds the data to output buffers. The output buffers are

powered from a separate supply, allowing support of different

logic families. During power-down, the outputs go to a high

impedance state.

APPLYING THE AD9214

Encoding the AD9214

Any high-speed A/D converter is extremely sensitive to the

quality of the sampling clock provided by the user. A Track/

Hold circuit is essentially a mixer. Any noise, distortion, or

timing jitter on the clock will be combined with the desired

signal at the A/D output. For that reason, considerable care has

been taken in the design of the ENCODE input of the AD9214,

and the user is advised to give commensurate thought to the clock

source. The ENCODE input is fully TTL/CMOS compatible, and

should normally be driven directly from a low jitter, crystal-

controlled TTL/CMOS oscillator.

The ENCODE input is internally biased, allowing the user to

ac-couple in the clock signal. The cleanest clock source is often

a crystal oscillator producing a pure sine wave. Figure 7 illustrates

ac coupling such a source to the ENCODE input.

ENCODE

LOW JITTER CRYSTAL SINE OR

PULSE SOURCE 1V p-p

AD9214

Figure 7. AC-Coupled Encode Circuit

Reference Circuit

The reference circuit of the AD9214 is configured by REFSENSE

(Pin 3). By externally connecting REFSENSE to AGND, the

ADC is configured to use the internal reference (~1.25 V), and

the REF pin connection (Pin 4) is configured as an output for

the internal reference voltage.

If REFSENSE is externally connected to AVDD, the ADC is

configured to use an external reference. In this mode, the REF

pin is configured as a reference input, and must be driven by an

external 1.25 V reference.

In either configuration, the analog input voltage range (either

1 V p-p or 2 V p-p as determined by DFS/Gain) will track the

reference voltage linearly, and an external bypass capacitor should

be connected between REF and AGND to reduce noise on the

reference. In practice, no appreciable degradation in performance

occurs when an external reference is adjusted

±5%.

DFS/GAIN

The DFS/GAIN (Data Format Select/Gain) input (Pin 2)

controls both the output data format and gain (analog input volt-

age range) of the ADC. The table below describes its operation.

Table I. Data Format and Gain Configuration

External

Differential

DFS/GAIN

Analog Input

Connection

Voltage Range

Output Data Format

AGND

1 V p-p

Offset Binary

AVDD

1 V p-p

Two’s Complement

REF

2 V p-p

Two’s Complement

Floating

2 V p-p

Offset Binary

Driving the Analog Inputs

The analog input to the AD9214 is a differential buffer. As

shown in the equivalent circuits, each of the differential inputs is

internally dc biased at ~AVDD/3 to allow ac-coupling of the

analog input signal. The analog signal may be dc-coupled as

well. In this case, the dc load will be equivalent to ~10 k

Ω to

AVDD/3, and the dc common-mode level of the analog signals

should be within the range of AVDD/3

±200 mV. For best dynamic

performance, impedances at AIN and A

IN should match.

Driving the analog input differentially optimizes ac performance,

minimizing even order harmonics and taking advantage of

common-mode rejection of noise. A differential signal may be

transformer-coupled, as illustrated in Figure 8, or driven from a

high-performance differential amplifier such as the AD8138

illustrated in Figure 9.

AIN

0.1 F

1:1

ANALOG

SIGNAL

SOURCE

AD9214

Figure 8. Single-Ended-to-Differential Conversion Using

a Transformer

Special care was taken in the design of the analog input section

of the AD9214 to prevent damage and corruption of data when

the input is overdriven. The optimal input range is 1.0 V p-p, but

the AD9214 can support a 2.0 V p-p input range with some degra-

dation in performance (see DFS/GAIN pin description above).

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